Abstract:Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-10… Show more
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