Purpose -Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations. Design/methodology/approach -The impacts of these interconnect process variations on circuit delay and cross-talk noises along with the two major sources of delays -parametric delay variations and global interconnect delays -have been discussed. Findings -Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non-deterministic. Originality/value -This paper usefully reviews process variation effects on very large-scale integration (VLSI) interconnect.

Process variation has emerged as a major concern in the design of circuits including interconnect pipelines in current nanometer regime. Process variation results in uncertainties of circuit performances such as propagation delay, noise and power consumption. Threshold voltage of a MOSFET varies due to changes in oxide thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of threshold variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced threshold variations on circuit delay is discussed for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

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Process variation has recently emerged as a major concern in the design of circuits including interconnect in current nanometer regime. Process variation leads to uncertainties of circuit performances such as propagation delay. The performance of VLSI/ULSI chip is becoming less predictable as MOSFET channel dimensions shrinks to nanometer scale. The reduced predictability can be ascribed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper provides an analysis of the effect of interconnect parasitic variation on the propagation delay through driverinterconnect-load (DIL) system. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies i.e 130nm, 70nm and 45nm. The comparison between three technologies interestingly shows that the effect of line resistive and capacitive parasitics variation on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitics. Propagation delay variation is from 0.01% to 0.04% and -4.32% to 18.1% due to resistive and capacitive deviation of -6.1% to 25% respectively.

Process variation in current nanometer regime has recently emerged as a major concern in the design of very large scale integrated (VLSI) circuits including interconnect. Process variation leads to many uncertainties on circuit performances such as propagation delay. With the shrinking channel dimensions of MOSFET to nanometer scale, the performance of VLSI/ULSI chip becomes less predictable. The predictability of circuit performance may be reduced due to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper presents the variation of propagation delay through driver-interconnect-load (DIL) system due to various effects of interconnect parasitic. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies of 130nm, 70nm and 45nm. The comparison between these three technologies extensively shows that the effect of line resistive and capacitive parasitic variations on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is observed from 0.01% to 0.04% and -4.32% to 18.1% due to resistive and capacitive deviation of -6.1% to 25% respectively.