Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Abstract

Chair of Advisory Committee: Dr. Duncan Moore Henry Walker As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology.In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated.Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

Estimating Power Supply Noise and its impact on path delay

“…As supply voltages are lowered, the sensitivity of path delay to power supply noise increases. It has been shown that a 10% decrease in the power/ground supply voltages increases path delay by about 8% in 180nm designs [1], 30% in 13 0nm technologies and a 1 % varia tion in power supply in 90nm leads to 4% increase in 276 delay respectively [2] [7]. This trend shows the growing need to study the effect of power supply noise on path delay.…”

“…The occurrence probabilities of voltage drops is then calculated by performing power analysis which is then used to estimate the extra delay induced by the IR -drop. Another statistical vectorless approach is proposed in [2] where supply voltage noise analysis is incorporated into static timing analysis (STA). The authors have estimated the noise based on different circuit models proposed in [9] with and with out the consideration of don't care bits.…”

Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise

“…However, the circuit size they reported [10] was limited, and its application to larger circuits was not clarified. Statistical treatment has been introduced into power supply noise-aware timing analysis [11]- [13] as another approach. Pant et al [11] estimated the voltage variations by convoluting statistically modeled current consumption and the impulse response of a power/ground network.…”

“…Jiang and Chen [12] first derived the average and standard deviation of all blocks and the correlation coefficients between the blocks, and they then estimated the delay. Kim and Walker [13] focused on the spatial correlation of power supply noise and proposed using principal component analysis (PCA) to model power supply noise. The path-delay distribution was then computed with uncorrelated variables.…”

“…We then carry out statistical STA (SSTA) using the derived statistical power/ground noise model. STA with a statistical model of power supply noise with PCA has been proposed by Kim and Walker [13]; however, as theirs was a preliminary work, several important issues, such as the nonGaussian distribution shape of variables and dynamic voltage fluctuations within the clock cycle, remain unsolved or have not been addressed. Furthermore, reducing the number of variables by using PCA due to the tight correlation between them has not been aggressively exploited to reduce CPU cost in STA.…”