Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise

Abstract

Abstract-Power supply noise is having increasingly more influence on timing, even though noise-aware timing analysis has not yet been fully established, because of several difficulties such as its dependence on input vectors and dynamic behavior. This paper proposes static timing analysis that takes power supply noise into consideration where the dependence of noise on input vectors and spatial and temporal correlations are handled statistically. We construct a statistical model of power supply voltage that dynamically varies with spatial and temporal correlation, and represent it as a set of uncorrelated variables. We demonstrate that power-voltage variations are highly correlated and adopting principal component analysis as an orthogonalization technique can effectively reduce the number of variables. Experiments confirmed the validity of our model and the accuracy of timing analysis. We also discuss the accuracy and CPU time in association with the reduced number of variables.

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

“…High-and mid-frequency power supply noise can be directly described by random variables with probabilistic formulations, as modeled in [29]. These random variables can be directly included in P in (1).…”

Interconnect Modeling: A Physical Design Perspective

“…Reference [20] proposes that spatially correlated components are converted into a set of uncorrelated variables (principal components) by using principal-component analysis (PCA), which drastically facilitates the consideration of correlation in SSTA. Recently, ways on how to consider a nonGaussian distribution [16] and environmental fluctuation [75] have been explored. In SSTA, delay variation of each gate and interconnect is often expressed using sensitivities to variation variables by first-order Taylor expansion.…”

Decoupling capacitance allocation for timing with statistical noise model and timing analysis

“…We here show impacts of decap position on the worst-case delay as an example. In this paper, the circuit delay is estimated by a noise aware SSTA [5], which gives a circuit delay distribution considering noise dependence on input patterns. We define the worst-case delay as · ¿ for a case, while other definitions delay also can be used, where and are the average and the standard deviation of the circuit delay, respectively.…”

“…[5] orthogonalizes the variables with principal component analysis, and derives a statistical model including the statistical information such as averages, standard deviations and correlation coefficients of the variables.…”

“…(1). The sensitivity of circuit delay to a power variable Ð Ý Î can be computed by SSTA considering power supply noise [5]. The sensitivity of a power variable to a decap Î can be calculated with a circuit simulation.…”