Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm<sup>2</sup>

Saito, Hisashi; Miyamoto, Yasuyuki; Furuya, Kazuhito

doi:10.1143/apex.3.084101

Cited by 16 publications

(19 citation statements)

References 17 publications

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“…The detailed TFET process flow can be found elsewhere. 9,29 The 250 nm thick molybdenum (Mo) was deposited on the n þ In 0.7 Ga 0.3 As layer and Cr/Ti dry etch masks were created on the top of Mo. A nano-pillar was formed after the dry etch of Mo and In 0.7 Ga 0.3 As layer.…”

Section: B Processing Of Self-aligned Gate Staggered Heterojunction mentioning

confidence: 99%

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Zhu

Jain

Vijayaraghavan

et al. 2012

Journal of Applied Physics

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Articles you may be interested inThe structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded In x Al 1-x As buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of >90% and >75% in the two orthogonal h110i directions with minimal lattice tilt was observed for the terminal GaAs 0.35 Sb 0.65 and In 0.7 Ga 0.3 As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of a and b dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of $3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of $4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibited higher dislocation density, as observed by cross-sectional transmission electron microscopy, resulting in the elongation of reciprocal lattice point of In 0.7 Ga 0.3 As channel and drain layers in the reciprocal space maps, while the InAs-like interface creates a defect-free interface for the pseudomorphic growth of the In 0.7 Ga 0.3 As channel and drain layers with minimal elongation along the Dx direction. The impact of the structural differences between the two interface types on metamorphic TFET devices was demonstrated by comparing p þ -i-n þ leakage current of identical TFET devices that were fabricated using GaAs-like and InAs-like interface TFET structures. Higher OFF state leakage current dominated by band-to-band tunneling process due to higher degree of defects and dislocations was observed in GaAs-like interface compared to InAs-like interface where type-II staggered band alignment was well maintained. Significantly lower OFF state leakage current dominated by the field enhanced Shockley-Read-Hall generation-recombination process at different temperatures was observed in InAs-like TFET structure. The fixed positive charge at the source/channel heterointerface influences the band lineup substantially with charge density greater than 1 Â 10 12 /cm 2 and the band alignment is converted from staggered gap to broken gap at $6 Â 10 12 /cm 2 . Clearly, InAs-like interface TFET structure exhibited 4Â lower OFF state leakage current, which is attributed primarily to the impact of the layer roughness, defect properties on the carrier recombination rate, suggesting great promise for metamorphic TFET devices for high-performance, and ultra-low power applications. V C 2012 American Institute of Physics.

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Section: B Processing Of Self-aligned Gate Staggered Heterojunction mentioning

confidence: 99%

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Zhu

Jain

Vijayaraghavan

et al. 2012

Journal of Applied Physics

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“…We believe that the large g o observed in the former structure [2] was caused by the gap between the gate electrode and the drain electrode. According to the results of a Monte Carlo simulation using DAMOCLES [4], the electric field originating from a propagating electron in a channel region is mainly terminated at a gate electrode in the region sandwiched by gate electrodes.…”

Section: Large Output Conductancementioning

confidence: 93%

“…Improvement in the performance of Si-CMOS by scaling is currently close to its physical limit. To surpass this physical limit, we have proposed a vertical InGaAs channel metal-insulator-semiconductor field-effect transistor (MISFET) with an InP/InGaAs heterostructure launcher and an undoped channel [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

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High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa

Kashiwano¹,

Hirai²,

Ikeda³

et al. 2013

Jpn. J. Appl. Phys.

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We fabricated a vertical metal–insulator–semiconductor field-effect transistor (MISFET) with a heterostructure launcher and an undoped channel. Vertical MISFETs exhibit a high drain current density; however, their large output conductance is a disadvantage for the open-circuit voltage gain. In a previous study, a maximum voltage gain of 4.0 was found in a vertical MISFET with a heavily doped drain region and a 45-nm-wide channel mesa. The heavily doped drain region and a narrower channel width are effective in reducing the output conductance. In this study, we fabricated a device with the heavily doped drain region and a 23-nm-wide channel mesa structure. It was observed that the output conductance decreased from 120 to 57 mS/mm at a drain current density of 0.3 MA/cm2 with a narrower channel mesa. The maximum open-circuit voltage gain increased from 4.0 to 5.7.

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“…Thus, we fabricated a GaAsSb/InGaAs vertical tunnel FET with a 26 nm wide body [6], as shown in Fig. 2 based on the InP/InGaAs vertical MOSFET process [14]. Transfer characteristics of devices are shown in Fig.…”

Section: Gaassb Source For Tunnel Fetsmentioning

confidence: 99%

InGaAs MOSFET source structures toward high speed/low power applications

Miyamoto

Kanazawa

Yonai

et al. 2014

26th International Conference on Indium Phosphide and Related Materials (IPRM)

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Short Abstract-High on-currents (I on ) and low off-currents (I off ) under low supply voltage are important for logic applications. A heavily doped InP source was introduced to demonstrate the existence of high I on in InGaAs MOSFETs, and I D = 2.4 mA/ m at V D = 0.5 V was observed. GaAsSb source was introduced in InGaAs tunnel FET to realize low I off . Narrow channel body was found to be essential for steep sub-threshold (SS) dependence, and a fabricated GaAsSb/InGaAs vertical tunnel FET with a 26 nm wide body showed steep SS. In addition, an InGaAs/InP super-lattice source was studied to consider the possibility of simultaneous high I on and low I off realization.

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Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm²

Cited by 16 publications

References 17 publications

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa

InGaAs MOSFET source structures toward high speed/low power applications

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Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm2

Cited by 16 publications

References 17 publications

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy

High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa

InGaAs MOSFET source structures toward high speed/low power applications

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Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm²