Fabrication of Self-Aligned Aluminum Gate Polysilicon Thin-Film Transistors Using Low-Temperature Crystallization Process

Abstract

The performance of scanning driver circuits fabricated with self-aligned aluminum gate polysilicon thin-film transistors (TFT's) is demonstrated. After the gate electrode patterning, the fabrication process temperature is kept below 400° C to enable the use of aluminum gate electrodes. The low-temperature crystallization phenomenon, which occurs when protons are implanted simultaneously with boron or phosphorus dopants, is employed to eliminate the 600° C activation-annealing process. A maximum clock frequency of about 2.0 MHz is achieved when the driver operating voltage is 24 V and the TFT channel length is 12 µm.

Low‐Temperature Polysilicon Oxide Thin‐Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V−1

“…[28,[39][40][41][42][43] The gate of LTPS TFT and LT-GI/HT-GI stack layer was patterned by wet and dry etching, respectively, with a PR covered on the n-type TFT region, as shown in Figure 1l and Figure S2a,b, Supporting Information. The p þ LTPS regions for S/D ohmic contact were B doped using an ion doping system using the self-align process, [44][45][46] as shown in Figure S2c,d, Supporting Information. The activation of this B-doped region was conducted by exposing the blue laser at room temperature, as shown in Figure S3, Supporting Information.…”

Improvement in Characteristics of Thin Film Transistors upon High-Pressure Steam Annealing

“…AP-CVD is able to provide uniform SiO 2 thin films on large substrates at low cost without the need for a complex vacuum system. 9) The high-pressure annealing system is usually made of a small metal pressure vessel. Therefore, it was difficult to apply it in the production of large LCD panels.…”