Extremely thin SOI (ETSOI) technology: Past, present, and future

Cheng, K.; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Kuss, J.; Edge, L. F.; Kimball, A. S.; Kanakasabapathy, S.; Schmitz, Stefan; Reznicek, A.; Adam, T.; He, Hongyu; Mehta, S.; Upham, A.; Seo, S.-C.; Herman, J.; Johnson, R.C.; Zhu, Yong; Jamison, P.; Haran, B.; Zhu, Zhengmao; Fan, Shuang; Bu, Hanyoung; Sadana, D. K.; Kozlowski, P.; O'Neill, J.; Doris, B.; Shahidi, G.

doi:10.1109/soi.2010.5641473

Cited by 20 publications

(14 citation statements)

References 13 publications

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“…The standard deviation mainly arises from a temperature gradient of about 3ºC across the wafer in the MOCVD system, which translates into a thickness gradient from the center of the wafers towards the bottom right edge. As with UTBB Silicon-on-insulator wafers, the thickness variability is a critical parameter since it directly translates into a V t shift with a rate of about 25 mV/nm [6]. Fig.…”

Section: A Substrate Fabricationmentioning

confidence: 99%

Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

Czornomaz

Daix

Kerber

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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In this work, we show for the first time that VLSIlike gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (S/D) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short L G .

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Section: A Substrate Fabricationmentioning

confidence: 99%

Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

Czornomaz

Daix

Kerber

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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“…10 If we consider the results presented in this work, we can use one metal with a low work function for the N-channel device, and four layer graphene/the same metal stack for a P-channel device, instead of using two different metals for N-and P-channel devices. In addition, extremely thin silicon on insulator technology utilizes single metal gate with mid-gap work function, 11 and three layers of graphene/metal stack could do the role.…”

mentioning

confidence: 99%

Work function tuning of metal/graphene stack electrode

Song¹,

Bong²,

Cho³

2014

Applied Physics Letters

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“…These devices feature a BOX of 25 nm down to a few nanometer that, when combined with UTB, results in very good electrostatic control of the gate and reduced variability originating from RDF effects [32]- [36]. UTB and BOX (UTBB) device performance is enhanced compared to extremely thin SOI (ETSOI) [37], both in terms of short channel effect control and S/D coupling due to the use of the thin BOX, and especially when combined with a ground plane doping scheme [38].…”

Section: Silicon-on-insulator and Shallow Trench Isolationmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Extremely thin SOI (ETSOI) technology: Past, present, and future

Cited by 20 publications

References 13 publications

Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

Work function tuning of metal/graphene stack electrode

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

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