2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) 2013
DOI: 10.1109/essderc.2013.6818839
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Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

Abstract: In this work, we show for the first time that VLSIlike gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (S/D) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. … Show more

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Cited by 20 publications
(11 citation statements)
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“…Above 250°C, Eb of Al2O3-Si pairs reaches almost 1 J/m 2 , whereas the values for SiO2-Si pairs remain below the estimated 'processable' threshold of 0.75 J/m 2 , in agreement with published data of SOITEC [3]. This confirms also our results for InGaAs-o-I where only bonding with Al2O3 worked, allowing us to successfully process MOSFET devices with such substrates [1,4]. By this token we have demonstrated that these InGaAs-o-I structures have excellent thermal stability to withstand the required device fabrication steps.…”
Section: Resultssupporting
confidence: 89%
“…Above 250°C, Eb of Al2O3-Si pairs reaches almost 1 J/m 2 , whereas the values for SiO2-Si pairs remain below the estimated 'processable' threshold of 0.75 J/m 2 , in agreement with published data of SOITEC [3]. This confirms also our results for InGaAs-o-I where only bonding with Al2O3 worked, allowing us to successfully process MOSFET devices with such substrates [1,4]. By this token we have demonstrated that these InGaAs-o-I structures have excellent thermal stability to withstand the required device fabrication steps.…”
Section: Resultssupporting
confidence: 89%
“…For es a high channel th (L g ), while for (W fin ) and a small d. f a high-mobility In 0.53 Ga 0.47 As-on-The impact of W fin vice performance vice cross section 1 (a), (b) and (c), ated on a nstructure obtained in [3]. The nped to 10 18 /cm 3 Fig. 2(a), it is clear that the gate control over the channel increases with the scaling of W fin, as the subthreshold swing (SS) reduces from 323 mV/dec at W fin = 200 nm to 108 mV/dec at W fin = 50 nm.…”
Section: Device Fabricationmentioning
confidence: 98%
“…1 has attracted lified fabrication ance [1], [2]. For es a high channel th (L g ), while for (W fin ) and a small d. f a high-mobility In 0.53 Ga 0.47 As-on-The impact of W fin vice performance vice cross section 1 (a), (b) and (c), ated on a nstructure obtained in [3]. The nped to 10 18 /cm 3 Fig.…”
Section: Device Fabricationmentioning
confidence: 99%
“…Substrate fabrication follows the method described in [16]. The III-V heterostructure is first grown by MBE on a semiinsulating InP donor wafer.…”
Section: Iii-v-oias Mosfetsmentioning
confidence: 99%