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In this work, we show for the first time that VLSIlike gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (S/D) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short L G .

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We demonstratehigh-performance self-aligned In 0.53 Ga 0.47 As-channel MOSFETs with effective channel length L EFF down to 20 nm, peak transconductance G MSAT over 2200 μS/μm at L EFF = 30 nm and supply voltage V DD = 0.5 V, thin inversion oxide thickness T INV = 1.8 nm, and low series resistance R EXT = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L EFF ≤ 30 nm and are among the best In 0.53 Ga 0.47 As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm 2 /Vs has progressively smaller impact as L EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures. I. INTRODUCTIONMany III-V materials have significantly better electron transport properties than Si, and therefore, have been actively investigated as the NFET solution for high-performance CMOS applications [1]. While most III-V research has been focused on HEMTs [2]-[18] or MOS-HEMTs [19]-[32], very few works have focused on MOSFETs [33]-[39]. MOSFETs are required for high performance and device density scaling because MOS-HEMTs have high overlap capacitance while HEMTs have large foot-print and high gate leakage [36]. Therefore, we have focused on self-aligned MOSFETs and processes that are not only manufacturable but also compatible with CMOS applications [36]. In this work, we demonstrate high-performance self-aligned In 0.53 Ga 0.47 As MOSFETs with L EFF down to 20 nm and peak G MSAT over 2200 μS/μm at V DD = 0.5 V. This work presents 2× higher performance compared to [36], and our devices are among the best In 0.53 Ga 0.47 As FETs in literature.

We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.