International audienceThe Ubaye valley, one of the most active seismic zones in the French Alps, was visited in 2003–2004 by a prolific and protracted earthquake swarm with a maximum magnitude M L = 2.7. The seismic activity clustered along a 9-km-long, 3- to 8-km-deep rupture zone which trends NW-SE across the valley and dips 80°SW. Focal mechanisms for the larger shocks show either normal faulting with a SW-NE trending extension direction or NW-SE strike slip with right lateral displacement. The activity initiated in the central part of the rupture zone, diffused to its periphery, and eventually concentrated in its southeastern deeper part. A permanent station situated above the swarm allowed us to monitor the entire phenomenon from its inception to its conclusion. The complete time series includes more than 16,000 events, with shocks down to magnitude M L = −1.3. It shows bursts of activity, separated by quiescent periods, with no well-defined subswarms as observed in other similar studies. The Gutenberg-Richter b value significantly varied between 1.0 and 1.5 in the course of the phenomeno

In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In 0.53 Ga 0.47 As MOSFETs with silicon. We first demonstrate that the transfer of highquality InGaAs / InAlAs heterostructures (t ch < 10 nm) can be achieved by direct wafer bonding and hydrogeninduced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600ºC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrierlowering (DIBL) against state-of-the-art III-V-o-I or TriGate FET data. IntroductionIn 0.53 Ga 0.47 As is a clear candidate to replace Silicon in MOSFETs for future low power logic application. The potential benefits have been demonstrated [1,2], although no meaningful benchmark to 22 nm Si technology has been done yet. However, very little work deals with cointegration methods where the fabrication of MOSFETs in a VLSI-like process is actually demonstrated [3]. Direct wafer bonding (DWB) can potentially be used for that purpose as UTB III-V devices could be fabricated on large scale wafers. Fig. 1 suggests that the thermal stability of bonded III-V heterostructures thinner than 80 nm will be sufficient to run a regular gate-first self-aligned MOSFET flow as reported in [4]. The transfer of thin In 0.53 Ga 0.47 As layers remains nevertheless a major roadblock, in particular to perform it with a cost effective process. DWB followed by substrate etching has been previously used [5], but is extremely costly and limited to small wafer sizes due to the maximum diameter of the III-V donor wafer. Fig. 2 describes a possible flow to fabricate UTB III-V target wafers based on hydrogen-induced thermal splitting, including recycle of the donor wafer. Implantation in In 0.52 Al 0.48 As buffer and etching selectivity between the layers of the III-V heterostructures are key ingredient for this process, alike etch selectivity between Si and SiO 2 can be used to fabricate ETSOI wafers.

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

We present and thoroughly compare band-structures computed with density functional theory,\ud tight-binding, k p and non-parabolic effective mass models. Parameter sets for the non-parabolic C,\ud the L and X valleys and intervalley bandgaps are extracted for bulk InAs, GaAs and InGaAs. We then\ud consider quantum-wells with thickness ranging from 3 nm to 10 nm and the bandgap dependence on\ud film thickness is compared with experiments for In0:53Ga0:47As quantum-wells. The impact of the\ud band-structure on the drain current of nanoscale MOSFETs is simulated with ballistic transport models,\ud the results provide a rigorous assessment of III–V semiconductor band structure calculation methods and\ud calibrated band parameters for device simulations

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In this work, we show for the first time that VLSIlike gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (S/D) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short L G .

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