An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

Djara, V.; Deshpande, V.; Uccelli, Emanuele; Daix, N.; Caimi, Daniele; Rossel, C.; Sousa, Marilyne; Siegwart, H.; Marchiori, Chiara; Hartmann, Jean‐Michel; Shiu, Kuen-Ting; Weng, C.-W.; Krishnan, M.; Lofaro, M.; Steiner, Rachel; Sadana, D. K.; Lubyshev, D.; Liu, A.; Czornomaz, Lukas; Fompeyrine, J.

doi:10.1109/vlsit.2015.7223668

Cited by 25 publications

(9 citation statements)

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“…By growing III-V layers on a Si donor wafer instead of on a lattice-matched III-V native donor wafer, III-V-on-insulator-on-Si substrates with any available wafer size can be realized [57,58]. Proof-of-principle demonstrations of 100 mm InGaAs-on-insulator [59] and 200 mm InGaAs-on-insulator wafers [60,61] were irst reported. In the fabrication process low described in Fig.…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

113

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Please note: Changes made as a result of publishing processes such as copy-editing, formatting and page numbers may not be reflected in this version. For the definitive version of this publication, please refer to the published source. You are advised to consult the publisher's version if you wish to cite this paper.This version is being made available in accordance with publisher policies. See http://orca.cf.ac.uk/policies.html for usage policies. Copyright and moral rights for publications made available in ORCA are retained by the copyright holders. U N C O R R E C T E D P R O O F ARTICLE INFO ABSTRACTMonolithic integration of III-V on silicon has been a scientifically appealing concept for decades. Notable progress has recently been made in this research area, fueled by significant interests of the electronics industry in high-mobility channel transistors and the booming development of silicon photonics technology. In this review article, we outline the fundamental roadblocks for the epitaxial growth of highly mismatched III-V materials, including arsenides, phosphides, and antimonides, on (001) oriented silicon substrates. Advances in hetero-epitaxy and selective-area hetero-epitaxy from micro to nano length scales are discussed. Opportunities in emerging electronics and integrated photonics are also presented.

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Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

113

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“…An alternative way of introducing these materials is by GeOI/IIIVOI (Germanium-on-Insulator/ III-V-on-Insulator) substrates [13,14]. In the case of Ge, these substrates can be fabricated either by bonding of a Ge donor wafer to an oxidized Si handle wafer or by the Ge condensation method, where a SiGe layer grown on a standard SOI (Silicon-On-Insulator) wafer is oxidized thereby turning the SiGe layer into a Ge-rich layer.…”

Section: Ge and Iii-v Integration On Si Substratesmentioning

confidence: 99%

“…Peak extrinsic transconductance as function of subthreshold swing measured at V DS = 0.5 V comparing different InGaAs (triangles) and InAs (rectangles) devices reported in the literature; FF = FinFET, GAA = Gate-All-Around and NW = nanowire[14,17,18,[42][43][44][45][46][47][48][49][50][51][52].…”

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confidence: 99%

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

Collaert

2016

JLPEA

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“…Recently, different strategies for III-V on silicon integration have been proposed. Strain-relaxed buffer layer growth and direct wafer bonding (DWB) [6,7], can enable large-area III-V-on-insulator substrates, as well as 3D heterogenous integration on processed substrates [8]. Selective epitaxial techniques make possible, instead, local integration of III-V crystals in pre-defined regions [9,10].…”

Section: Introductionmentioning

confidence: 99%

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

et al. 2018

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III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

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An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

Cited by 25 publications

References 2 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

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