Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Abstract

Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm gate length. We have observed that for low-temperature analog operation, high-k gate dielectric is not a viable option at this gate length, as the intrinsic dc gain (A V 0 ) decreases with increase in dielectric constant of the gate dielectric because of a pronounced increase in fringeinduced barrier lowering. On the other hand, dual-k spacer-based underlap FinFET is a promising candidate in improving critical analog figures of merit (FOM), such as intrinsic dc gain (A V 0 ), cutoff frequency (f T ), and maximum oscillation frequency (f max ) as the temperature is reduced. More so, the percentage increase in FOM of dual-k FinFET is enhanced at lower temperature as well as at lower gate length. Therefore, dual-k spacer underlap FinFET can be a possible solution for further device scaling at low-temperature environment.Index Terms-Carrier mobility, dual-k spacer, figures of merit (FOM), low-temperature operation.

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

“…2. While doing the device simulation, the following models are included in the simulation setup: Lombardi mobility model, Philips unified mobility model, band to band auger recombination, Shockley-Read-Hall recombination/ generation model, and old slotboom bandgap narrowing phenomenon [20,22]. To include quantum confinement effect, MLDA quantisation model is included.…”

Comparative study of 16‐order FIR filter design using different multiplication techniques

“…Digital filters remove noise and interference from the original signal and are used for modification of various attributes of the signal. Digital filters are more accurate, more versatile and highly stable, thereby a preferred technique over its analogue counterpart [3].Optimisation of area, delay and power of both digital and analogue building blocks becomes a challenging task with increase in circuit components [4,5]. One such application is designing FIR filter, which further complicates the situation with increase in its filter order [6].…”

Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

“…In the literature, there are many works that compare the performance of bulk planar and SOI FinFETs [9,10,15]. Since FinFETs appear to have a potential for analog applications [6,[15][16][17][18] many studies evaluated in detail the analog performance of Fin-FETs from different perspectives, mainly in SOI structures, such as: dual-dielectric constant (k) spacer underlap for n-and psubstrate types [19], underlap devices at low temperature operation [20], gate-underlap design effects [21], the influence of strain techniques [22] and the impact of the fin width on digital and analog performances of n-type devices [23]. On the other hand, few studies focus on the comparison of the bulk and SOI FinFET structures.…”