Comparative study of 16‐order FIR filter design using different multiplication techniques

Mittal, Anubhuti; Nandi, Ashutosh; Yadav, Disha

doi:10.1049/iet-cds.2016.0146

Cited by 57 publications

(36 citation statements)

References 22 publications

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“…Mittal et al [14] proposed a different multiplication approach based 16 th order FIR filter. This method was optimized filter area, power and delay based on approach such as FIR filter coefficient with FIR filter input.…”

Section: Literature Workmentioning

confidence: 99%

“…The constraints shift the properties of the degraded signals and the theoretical issues related to their properties [3]. For an efficient filter design, optimization should be done in architecture to improve filter performances by power consumption, area and delay which can be achieved by proper selection of multiplier and adder techniques [4]. The fixed coefficient FIR can be designed with either SCM or MCM schemes.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

Anumothu*,

Harikishore

2020

IJITEE

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In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR.

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Section: Literature Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

Anumothu*,

Harikishore

2020

IJITEE

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“…Mittal et al [19] designed a low power and high speed 16-order FIR filter. This method reduced filter's area, power and delay by using adder, shifter WTM and Vedic multiplier algorithms.…”

Section: Literature Surveymentioning

confidence: 99%

Low Area VLSI implementation of CSLA for FIR Filter Design

Kumar¹,

Gangappa²

2019

IJIES

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Finite Impulse Response (FIR) filter is a major building block in Digital Signal Processing (DSP) system. The conventional FIR filters are implemented by utilizing a normal adder, which consumes more area. Minimizing the hardware utilization of the adder is a significant challenge in FIR filter design. Generally, complexity of the FIR filter is dominated by the adder. So, an efficient FIR filter was designed with the help of Carry Select Adder (CSLA) to reduce area and hardware complexity of the accumulation block. The area has been reduced by using CSLA that is very significant idea while designing a less area filter. The proposed method named as Low Area-CSLA-FIR (LA-CSLA-FIR) filter. The LA-CSLA-FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) on different devices such as Virtex-4, Virtex-5 and Virtex-6 by using Verilog code. The experimental results of the LA-CSLA-FIR filter design reduced average the FPGA device utilization: 15.38 % of LUTs, 8% of flip flops and 8% of slices on Virtex-5 compared to existing filter designs.

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“…To scale back the hardware value, the hardware place should be optimized. Multipliers eat the foremost amount of space in a very FIR filter out the layout. The modified procedure of low power FIR channel configuration comprises of productors, postpone components, and addition components, acknowledged utilizing reversible rationale gates.…”

Section: Proposed Fir Filter Designmentioning

confidence: 99%

Implementation of FIR filter using reversible modified carry select adder

Sekar

Sasipriya²

2018

Concurrency and Computation

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Summary Any arithmetic operation can be performed using the method of Reversible process which allows minimum arithmetic execution. An essential scenario for achieving this condition is the arithmetic design connections should be of one to one. The Finite Impulse Response (FIR) Filter is that the indispensable part to design digital signal processing framework. The adders and multipliers assume an urgent part in FIR filter while thinking about the power. In this paper, an effective FIR filter is actualized utilizing minimum power reversible modified SQRT carry select adder utilizing Brent Kung adder and D latch. Reversible logic has developed as another outline method to the customary rationale, prompting low power consumption and lesser circuit region. For accomplishing low power, reversible rationale method of task is implemented inside the style. The proposed configuration accomplishes three‐overlap benefits in terms of Area‐power‐delay. From the combination comes about, the newly portrayed minimum power FIR filter configuration shows low power of 294641.397 nW when contrasted with regular outline. Proposed FIR Filter is reenacted by utilizing rhythm device as cadence tool.

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Comparative study of 16‐order FIR filter design using different multiplication techniques

Cited by 57 publications

References 22 publications

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

Low Area VLSI implementation of CSLA for FIR Filter Design

Implementation of FIR filter using reversible modified carry select adder

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