Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures

Abstract

a b s t r a c tThis paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (A V ) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25°C to 150°C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (A V ) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p-and n-type FinFET structures. In addition, the pFinFETs showed slightly larger A V values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.

Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes

“…The mobility for the STI first approach is fin width-independent, as already presented in [27] at room temperature. On the other hand, for STI last the μ eff is clearly fin width-dependent, revealing that there is a strong sidewall contribution, since the narrower the fin, the stronger is the electrostatic control inside the fin by the sidewall [28]. Additionally, the low-field hole mobility value for the 〈100〉 plane is inferior to the 〈110〉 one [29].…”

High Performance Amorphous IGZO Thin-Film Transistor Based on Alumina Ceramic

“…The interstitial oxygen formed by the excitation of the oxygen atoms, and the increase in the number of these intrinsic point defects caused by thermal excitation, result in an increase of SS. It is evident that with the increase of temperature, the device switching performance deteriorates [33]. Fig.…”

Performance characteristics of p-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

“…Of course, if the etch process can't be controlled well, these benefits will be discounted. Through this analysis, the S/D extension length contributing to the FinFET device performance [24][25][26] can be sensed well. This helpful information in FinFET fabrication offers the manufacturing team in decision of chosen OFF or ON current in the need of different HPC IC products.…”