Effects of halo implant on hot carrier reliability of sub-quarter micron MOSFETs

Das, Aloke Kumar; De, Han; Misra, Veena; Venkatesan, S.; Veeraraghavan, S.; Foisy, M.

doi:10.1109/relphy.1998.670539

Cited by 2 publications

(1 citation statement)

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“…Recently, it has been shown that halo implants can provide such short-channel control for Ge pMOSFETs [4], [8] at the cost of a higher drain-to-well leakage current with respect to silicon devices [9]. For the silicon case, it is known [10] that halo implant increases hot-carrier (HC) degradation. To date, the most promising Ge results have been obtained using a Si-passivation layer where a few monolayers (MLs) of Si are epitaxially grown on the Ge surface immediately prior to gate stack formation [3], [4], [7], [8], [11].…”

Section: Introductionmentioning

confidence: 99%

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Maji

Crupi

Amat

et al. 2009

IEEE Trans. Electron Devices

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Abstract-In this paper, a comprehensive study of hotcarrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.Index Terms-Germanium, high-k, hot carrier (HC), impact ionization, negative bias temperature instability (NBTI), pMOSFET.

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Section: Introductionmentioning

confidence: 99%

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Maji

Crupi

Amat

et al. 2009

IEEE Trans. Electron Devices

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Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

1999

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Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hotelectron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, highpressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (Q BD ), hot-electron degradation, and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.

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Effects of halo implant on hot carrier reliability of sub-quarter micron MOSFETs

Cited by 2 publications

References 1 publication

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

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