No abstract
We have developed a new NBTI test structure with that of an unstressed RO, improving sensitivity and comprising differential pairs of ring oscillators with stages of reducing vulnerability to sources of common mode error. A various circuit types. For stages consisting of inverters driving digital beat frequency circuit is provided for high resolution p-FET passgates, the gates of which are set at an adjustable DC measurements of frequency shifts in response to low voltage potential, this structure allows high resolution absolute stresses stresses of short duration or relaxation after stress, measurement of the average Vt shift of a large number (-100) . '. .. . f product representative p-FETs in response to very short as well reduirngthe s nsitylmit imosed b or e le, A as traditional long duration pure NBTI AC or DC environmental or instrumentation-related noise floor. A voltage/temperature stresses. special NBTI-sensitive RO stage design is introduced to measure only the effect of NBTI, excluding other Index Terms-Circuit reliability, circuit modeling, CMOS degradation mechanisms such as HC, and to directly reveal integrated circuits, MOSFETs the p-FET Vt shift, with no reliance on simulation. Measured results represent values averaged over I00 p-FETs, thereby I. INTRODUCTION minimizing the impact of random variability in discrete In CMOS products, circuit performance degradation with devices. Data from 90 nm and 65 nm CMOS technology time is an important reliability issue. One of the degradation nodes are shown along with a comparison of measured Vt mechanisms is induced by Negative Bias Temperature shift of individual p-FETs and RO p-FET Vt shift, verifying Instability, NBTI, which, as a result of interface traps and the integrity of the RO approach. positive oxide charge generation, manifests itself as a shift in threshold voltage, Vt, in p-FETs [1]. The effect is typically II. DESCRIPTION OF TEST STRUCTURE studied in an offline setting in discrete MOSFETs under The NBTI test structure has two new and important circuit accelerated stress conditions of elevated voltage and features compared with previous RO-based approaches in the temperature. A large number of such devices have to be literature [4, 5]. First, it utilizes a differential measurement measured to account for statistical variations [2]. The impact technique in which the frequency of the stressed RO is on product performance at end-of-life is estimated by directly compared with that of an unstressed companion. deriving the acceleration factors to obtain the p-FET Vt shift Second, it incorporates a unique RO stage design that enables and by including this Vt shift in chip timing models. The a pure NBTI stress application, AC or DC, as well as a direct analysis is further complicated by the fact that a part of the Vt absolute measurement of the stress induced p-FET Vt shift. shift under accelerated conditions is recovered by relaxation mechanisms after the stress is removed [1]. It is therefore Fig. 1 shows a pair of ROs, RO1 and R02, along with a be...
I. AbstractA high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (V dd =1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 µm 2 . II. Technology DescriptionThe major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated. III. FEOL Performance ResultsA plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-cur...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.