Differential block frequency compensation for low‐power multistage amplifiers

Asiyabi, Tayebeh; Torfifard, Jafar

doi:10.1002/jnm.2517

Cited by 5 publications

(1 citation statement)

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“…For instance, AC boosting compensation (ACBC) [2], active feedback frequency compensation (AFFC) [3], and differential feedback path (DFP) [7] have been introduced to enhance amplifier parameters compared with basic NMC and RNMC approaches. Commercial tendencies have led to even more complicated amplifiers to satisfy speed and power demands [18][19][20][21][22][23][24][25][26][27][28][29]. For instance, Ref.…”

Section: Introductionmentioning

confidence: 99%

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

et al. 2023

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Multistage amplifiers have become appropriate choices for high‐speed electronics and data conversion. Because of the large number of high‐impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500‐pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five‐stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.

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Section: Introductionmentioning

confidence: 99%

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

et al. 2023

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A high‐performance CMOS four‐stage amplifier

Zanjani

Asiyabi

Biabanifard³

2019

Int J Numerical Modelling

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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

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