The advancement of CMOS technology limits designers' options for multi‐stage configurations as a promising alternative to cascade structures. The main issue of designing multi‐stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three‐stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole‐zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using 0.180.25emμm0.25em CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of 1050.25emdB, a gain‐bandwidth product of 4.80.25emMHz, a phase margin of 72°, and a power dissipation of 3600.25emμW. The high performance of the proposed three‐stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.
Multistage amplifiers have become appropriate choices for high‐speed electronics and data conversion. Because of the large number of high‐impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500‐pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five‐stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.
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