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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

A new power-efficient frequency compensation structure is presented, named the differential block frequency compensation (DBFC) topology. The new compensation technique employs a fully differential stage to organize feedforward and feedback paths. The DBFC technique relieves feedforward and able to amplify feedback currents to move poles and zeros accordingly, which leads to pole-zero cancelation scenario. Initially, the proposed structure uses only small compensation capacitance, which means very compact and refined design. The proposed circuit along with several state-of-the-art designs from the literature have been extensively analyzed and compared together. The results reveal the improvement regarding to figure of merit factors, which highlight size of compensation circuits, stability, and power dissipation issues. Moreover, the gain-bandwidth product increases more than 30 times than of other compared circuits. KEYWORDS differential block frequency compensation, low power, low voltage, operational transconductance amplifier

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.