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In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.

In this article, a new configuration of a three-stage Complementary metaloxide-semiconductor (CMOS) operational transconductance amplifier (OTA) isproposed. It removes the feedforward path while simultaneously amplifying the feedback path in the compensation network. Also, the proposed circuit uses only one small compensation capacitor which makes it appropriate regarding die area. The approach behind is demonstrated through a successful design using 0.18-μm CMOS technology. In fact, the simulated OTA shows better performance in comparison with other methods and achieved 20.2 MHz, 82 , and 124 dB as gain-bandwidth product, phase margin, and DC gain, respectively, and consumes 545 μW @ 1.8 V. K E Y W O R D S

This article presents a set of ring oscillators design using three types of inverters. Symbolical delay calculations are performed and dependency on the supply voltage is investigated for each inverter. Based on delay descriptions, combined structures show the potential to behave more stable than simple structures. Mostly combined structures reduce speed as the cost of realizing less sensitive circuits. The analysis yields more robust ring oscillators vs noisy conditions, specifically supply voltage ripples and temperature deviations. Based on calculations, seven possible structures are simulated exploiting TSMC 0.18 μm CMOS. Additionally, combined ring oscillators are more robust against supply voltage ripples and temperature variations. The cost of this robustness is reduced oscillation frequency value. Based on the structure, in CMOS technology expresses 3% oscillation frequency deviation against 30% supply variation. The new combined structures demonstrate high potential to be used in larger circuits and systems like phase loops and clock generator.