In this article, a new configuration of a three-stage Complementary metaloxide-semiconductor (CMOS) operational transconductance amplifier (OTA) isproposed. It removes the feedforward path while simultaneously amplifying the feedback path in the compensation network. Also, the proposed circuit uses only one small compensation capacitor which makes it appropriate regarding die area. The approach behind is demonstrated through a successful design using 0.18-μm CMOS technology. In fact, the simulated OTA shows better performance in comparison with other methods and achieved 20.2 MHz, 82 , and 124 dB as gain-bandwidth product, phase margin, and DC gain, respectively, and consumes 545 μW @ 1.8 V.
K E Y W O R D S
This article presents a set of ring oscillators design using three types of inverters. Symbolical delay calculations are performed and dependency on the supply voltage is investigated for each inverter. Based on delay descriptions, combined structures show the potential to behave more stable than simple structures. Mostly combined structures reduce speed as the cost of realizing less sensitive circuits. The analysis yields more robust ring oscillators vs noisy conditions, specifically supply voltage ripples and temperature deviations. Based on calculations, seven possible structures are simulated exploiting TSMC 0.18 μm CMOS. Additionally, combined ring oscillators are more robust against supply voltage ripples and temperature variations. The cost of this robustness is reduced oscillation frequency value. Based on the structure, in CMOS technology expresses 3% oscillation frequency deviation against 30% supply variation. The new combined structures demonstrate high potential to be used in larger circuits and systems like phase loops and clock generator.
Purpose
The purpose of this paper is to investigate a more robust ring oscillator. Less sensitivity to power supply variations is a target. This is important since low-quality ring oscillators could be exploited in numerous systems to reduce die costs.
Design/methodology/approach
The method in this work is large signal analysis. Delay time as the large signal parameter is calculated symbolically to explore dependency on a power supply voltage. Then simulations are performed to make a comparison. In this work, mathematical justifications are verified via HSPICE circuit simulator outputs, while 0.18 µm TSMC CMOS technology is exploited.
Findings
At least two combined configurations are presented with higher robustness. These circuits are more appropriate in noisy conditions. Both theoretical calculations and simulation results verify less sensitive oscillation against supply voltage ripples and temperature variations.
Originality/value
Introducing a band-switched inverter in combined configurations is contribution. In this way, three structures are presented which both show higher stability in oscillation frequency. The band switched delay time calculations are quite new and also the validity of the symbolical delay time approach is verified by circuit simulations.
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