Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

Abstract

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μeff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 × 1012 cm2/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μeff. On the other hand, at strong Ninv (= 1.5 × 1013 cm2/V∙s), GAA NW-FET shows 10 times higher dμeff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport.

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

“…Gate-all-around (GAA) Si nanowire (NW) FET, which is regarded as the most likely candidate to replace FinFET in the next CMOS technology nodes [11], [12] with reduced short channel effects (SCE), lower power dissipation and higher integration density, is a promising candidate to overcome the enhanced band tail effect (localized and mobile states) at Cryo-T. The superior gate control ability in aggressively scaled nanowires with GAA structure could effectively suppress the 0741-3106 © 2022 IEEE.…”

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

“…Some new kinds of devices [ 14 , 15 , 16 ] have now been reported for MOSFET alternatives. Gate-all-around (GAA) silicon nanowire (Si NW) or nanosheet (NS) field effect transistor (FET) is regarded as the most likely candidate to replace FinFET in the next CMOS technology nodes [ 17 , 18 ], and has better gate control ability for scaling down with lower power dissipation and higher integration density as well as the application for cryo-CMOS. In addition, the quantum confinement effect will be more pronounced in the small-size GAA NW devices.…”

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in situ deposited Al2O3/Y2O3 as a gate dielectric

“…Therefore, the depletion capacitance (C dep = dQ dep /dψ s ∼ 0) is negligibly small in these devices. 31) Furthermore, for ultra-thin channel devices, the D it has less impact on SS; the SS of the fully depleted devices was further reduced as the channel thickness or diameter of the nanowire decreased, 20,32) which may be caused by quantum confinement. These effects have resulted in SS close to 60 mV dec −1 in the non-planar ultra-thin body devices.…”