Comparative analysis of conventional and statistical design techniques

Abstract

We explore the power benefits of changing a microprocessor path histogram through circuit sizing based on statistical timing analysis and optimization (STAO) versus a deterministic timing approach that uses statistical design to establish a global guardband followed by conventional optimization (SDGG). Using an analytical modeling approach, we quantify the differences in total power between the two approaches while maintaining an equivalent performance distribution. For a relative 1σ random WID stage delay variation of 5% and representative microprocessor critical paths, the analysis indicates that the STAO approach enables ∼2% power reduction over the SDGG approach. To achieve a 4% and 6% power reduction through the STAO approach, the process variation needs to increase by a factor of 2x and 4x, respectively.

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

“…Interestingly, this increase in the number of good dies comes without any assumption of improved manufacturing capability (i.e., variability reduction). In addition, statistical analysis and optimization methodologies may not provide, by themselves, sufficient improvement of circuit metrics (e.g., [25] cites a 2% power reduction from statistical optimization; see also [26]). Therefore, our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.…”

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation

“…Silicon data at 65nm and below suggest that characterization of die-to-die variation and spatial correlations is essential to statistical design flows. 3 An even more basic issue is whether sufficient ROI can be shown for statistical design approaches; e.g., [4] showed limited impact of statistical power optimization. Intuitively, statistical design will have only limited impact with respect to "sum" objectives such as power, as opposed to "max" objectives such as timing.…”

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

“…Statistical timing analysis has become an important verification tool at circuit and system level design [3], and the study of system timing variability as a function of device and circuit variation is of considerable present interest [4]. To first order, signal propagation time is determined by CV /I .…”