A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimization algorithm has been used here. This algorithm is guaranteed to find the exact solution to the convex programming problem. We have also improved upon existing methods for computing the circuit delay as an EImore time constant, to achieve higher accuracy. CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm.

In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by rst computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to nd an optimal design point at which all of the circuit speci cations are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multi-criteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and e ciency.

Motivated by the potentially large number of devices and simulations involved in optoelectronic system design, and the associated need for compact optoelectronic device models, we present a simple thermal model of vertical-cavity surface-emitting laser (VCSEL) light-current (LI) characteristics based on the laser rate equations and a thermal offset current. The model was implemented in conventional SPICE-like circuit simulators, including HSPICE, and used to simulate key features of VCSEL LI curves, namely, thermally dependent threshold current and output-power roll-over for a range of ambient temperatures. The use of the rate equations also allows simulation in other non-dc operating regimes. Our results compare favorably to experimental data from three devices reported in the literature.

The increasing interest in vertical-cavity surfaceemitting lasers (VCSEL's) requires the corresponding development of circuit-level VCSEL models for use in the design and simulation of optoelectronic applications. Unfortunately, existing models lack either the computational efficiency or the comprehensiveness warranted by circuit-level simulation. Thus, in this paper we present a comprehensive circuit-level model that accounts for the thermal and spatial dependence of a VCSEL's behavior. The model is based on multimode rate equations and empirical expressions for the thermal dependence of the activelayer gain and carrier leakage, thereby facilitating the simulation of VCSEL's in the context of an optoelectronic system. To confirm that our model is valid, we present sample simulations that demonstrate its ability to replicate typical dc, small-signal, and transient operation, including temperature-dependent lightcurrent (LI) curves and modulation responses, multimode behavior, and diffusive turn-off transients. Furthermore, we verify our model against experimental data from four devices reported in the literature. As the results will show, we obtained excellent agreement between simulation and experiment.

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Even with the use of variable transformations, quantum-well (QW)-laser models based on the standard rate equations and a linear gain-saturation term can possess multiple dc solution regimes for nonnegative values of injection current. In this paper, we demonstrate analytically that rate-equationbased models that employ more realistic gain-saturation terms can be transformed so that they do indeed possess a unique solution regime. We also present circuit-level implementations of these models suitable for use in SPICE. Institute of Technology, Lausanne, Switzerland. His research interests include VLSI design methodologies and optimization for performance, reliability and manufacturability, modeling and simulation of semiconductor devices and circuits, high-speed optoelectronic circuits, and fully optical network systems. He holds four patents and has published more than 250 papers and coauthored six books: Design Automation for Timing-Driven Layout Synthesis (New York: , the University of Arizona, and the National Science Foundation. Prior research activities were in the areas of gas discharge lasers, gas phase nonlinear optics, FIR optically pumped lasers, and optical nonlinearities in semiconductor quantum wells. Currently, his research is addressing III-V device design and fabrication issues for photonic circuit applications and the application of MEMS technologies to optical network switching devices.

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