A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimization algorithm has been used here. This algorithm is guaranteed to find the exact solution to the convex programming problem. We have also improved upon existing methods for computing the circuit delay as an EImore time constant, to achieve higher accuracy. CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm.

It is well known that the smallest eigenvalue of the adjacency matrix of a connected d‐regular graph is at least − d and is strictly greater than − d if the graph is not bipartite. More generally, for any connected graph G = (V, E), consider the matrix Q = D + A where D is the diagonal matrix of degrees in the graph G and A is the adjacency matrix of G. Then Q is positive semidefinite, and the smallest eigenvalue of Q is 0 if and only if G is bipartite. We will study the separation of this eigenvalue from 0 in terms of the following measure of nonbipartiteness of G. For any S ⊆ V, we denote by emin(S) the minimum number of edges that need to be removed from the induced subgraph on S to make it bipartite. Also, we denote by cut(S) the set of edges with one end in S and the other in V − S. We define the parameter Ψ as. The parameter Ψ is a measure of the nonbipartiteness of the graph G. We will show that the smallest eigenvalue of Q is bounded above and below by functions of Ψ. For d‐regular graphs, this characterizes the separation of the smallest eigenvalue of the adjacency matrix from −d. These results can be easily extended to weighted graphs.

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This paper reviews the step-response of the semi-innite distributed RC line and focuses mainly on the step-response of a nite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present d a y i n tegrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest rst order lumped -approximation to the nite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% thresholdcrossing times.

Linear ordering has applications in Standard Cells and Gate Array placement. This paper presents a new approach to linear ordering based on the new Stochastic Evolution (SE) methodology for solving intractable combinatorial optimization problems [l]. The SE heuristic performs better than Kang's heuristic [2] and Simulated Annealing [3]. In many cases, The SE heuristic was significantly better than Kang's heuristic, and an order of magnitude better than Simulated Annealing.