Fast effective heuristics for the graph bisectioning problem

Saab, Youssef; Rao, Vasant B.

doi:10.1109/43.45859

Cited by 18 publications

(11 citation statements)

References 17 publications

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“…One of major OTDM is to partition the graph into a given or any number of parts [75,[77][78][79][80][81][82][83][84]. The task of graph partitioning has many practical applications.…”

Section: The Analysis Of Genetic Algorithms Of Graph Partitioning On mentioning

confidence: 99%

“…-those proposed by А. N. Melikhov, L. S. Bershtein, V. M. Kureichik; V. Kernigan, S. Linn and their improved heuristics [41,82]; -formation of the minimal sets [75]; -simulated annealing [34]; -of S. Fiducceo, R. Mateuss and their modifications [83]; -matrix-based [84]; -of random assignments [79]; -of evolution simulation [24,37,38,88].…”

Section: The Analysis Of Genetic Algorithms Of Graph Partitioning On mentioning

confidence: 99%

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Genetic Algorithms for Applied CAD Problems

Malioukov¹,

Kureichik²,

Malioukov³

2009

Studies in Computational Intelligence

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“…One of major OTDM is to partition the graph into a given or any number of parts [75,[77][78][79][80][81][82][83][84]. The task of graph partitioning has many practical applications.…”

Section: The Analysis Of Genetic Algorithms Of Graph Partitioning On mentioning

confidence: 99%

Section: The Analysis Of Genetic Algorithms Of Graph Partitioning On mentioning

confidence: 99%

Genetic Algorithms for Applied CAD Problems

Malioukov¹,

Kureichik²,

Malioukov³

2009

Studies in Computational Intelligence

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“…The program was tested against several benchmark circuits. These circuits were used by Saab and Rao to test their circuit partition algorithm [10]. The results of our experiments are shown in Figure 5; the execution time in includes both CPU time as well as I/O time.…”

Section: Placement On Alliantmentioning

confidence: 99%

“…The program was tested against circuits provided by Saab and Rao [10]. In these circuits, problem sizes range from 20 cells up to 350 cells.…”

Section: Partition On Alliantmentioning

confidence: 99%

Solving Physical Design Problems on a Vector Machine

Ravikumar

The Fifth International Conference on VLSI Design

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In this paper, we describe parallel algorithms for two physical design problems. The target machine is the Alliant FX/80, which is a shared-memory multiprocessor with up to 8 advanced computational elements which are individually capable of vector operation. First, we describe the parallel implementation of an r-dimensional circuit placement algorithm. The objective of the placement problem is to arrange n logic blocks in an r-dimensional space so as to minimize the length of the interconnect wiring among the blocks. The problem is known to be NP-complete, and the numerical optimization technique presented in this paper finds a local optimum solution. Next, we discuss a parallel version of Kernighan and Lin's algorithm for the two-way circuit partition problem. Given n logic blocks and their connectivity matrix C, the problem is to generate a balanced two-way partition of the blocks such that the wiring across the partition is minimum. The partition problem is NPcomplete, but the Kernighan-Lin heuristic algorithm generates a near-optimal solution.

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“…No polynomial time algorithms are known for approximating the bisection width to within a constant factor, even for the case of planar graphs [LT79]. As a result, most practitioners use heuristics which find near optimal bisections most of the time [GB83,SC88,SR90].…”

Section: Introductionmentioning

confidence: 99%

Iterative compaction: an improved approach to graph and circuit bisection

Haralambides¹,

Makedon²

Proceedings of the European Conference on Design Automation.

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Given a graph G=(V,E), graph bisection is the problem of finding a partition of the vertex set V into two equal-sized subsets V I and V 2 so that the number of edges between them is minimized. This problem has important applications in circuit wtitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. We mroduce a new heuristic approach, called Iterative Compacnon (IC), which employees a node degree based matching and uerative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results.

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Fast effective heuristics for the graph bisectioning problem

Cited by 18 publications

References 17 publications

Genetic Algorithms for Applied CAD Problems

Genetic Algorithms for Applied CAD Problems

Solving Physical Design Problems on a Vector Machine

Iterative compaction: an improved approach to graph and circuit bisection

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