Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

Abstract

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping.

Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants

“…As geometries of MOSFET shrink, the intrinsic device parameter variations such as line edge roughness [13], the 3 Author to whom any correspondence should be addressed. granularity of the polysilicon gate [14,15], random discretedopant effects [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] have brought significant impacts on device characteristic fluctuations; it is imperative to model and mitigate them in silicon technology. Furthermore, various randomness effects resulting from the random nature of manufacturing process, such as ion implantation, diffusion and thermal annealing, have induced significant fluctuations in the electrical characteristics in nanometer scale (nanoscale) MOSFETs.…”

“…The number of dopants is of the order of tens in the depletion region of a nanoscale MOSFET whose influence on device characteristic is large enough to be distinct [16]. Various random dopant effects have been recently studied in both experimental and theoretical approaches [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32]. Fluctuations in characteristics are caused not only by a variation in an average doping density, which is associated with a fluctuation in the number of impurities, but also with a particular random distribution of impurities in the channel region.…”

“…Fluctuations in characteristics are caused not only by a variation in an average doping density, which is associated with a fluctuation in the number of impurities, but also with a particular random distribution of impurities in the channel region. Diverse approaches have recently been reported to study fluctuation-related issues in semiconductor devices [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] and a digital integrated circuit [31][32][33][34][35]. So far, the attention is mostly drawn on the fluctuations in threshold voltage and dc characteristics.…”

Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit

“…The C−V curves are horizontally shifted due to the variation of the effective channel doping concentration, which may be described using the corresponding V th parameters in a compact model. Additionally, the shape of the curves is changed due to the randomness of the dopant position in the channel, which affects the shape of the depletion region [5]. To the best of the authors' knowledge, the fluctuation in the gate capacitance C g has not yet been modeled, and a coupled device-circuit simulation must be performed to estimate it.…”

“…However, less attention has been paid to timing characteristic fluctuations of active devices caused by random dopants. Additionally, the randomness of dopant positions in devices makes the fluctuation of the gate capacitance of a device nonlinear and difficult to model using the present compact models [5]. Thus, this brief presents a large-scale statistically sound coupled device-circuit simulation approach to analyze the random dopant effect in nanoscale complementary metal-oxide-semiconductor (CMOS) circuits, concurrently capturing the fluctuations associated with the number and positions of discrete dopants.…”