Analytical thermal placement for VLSI lifetime improvement and minimum performance variation

Abstract

Abstract. We discuss aspects of silicon quality and value left on the table by current physical implementation and manufacturing handoff flows. These aspects include the following. (1) Proper expectations with respect to guardbanding of process, statistical design, and gaps in nascent flows. (2) How manufacturing variability should be deal with by design flows, e.g., with approaches less dogmatic than traditional "correct by construction" (prevention) or "construct by correction" (cure). (3) Opportunities to differentiate with physical implementation 'glue' technologies in place-and-route. (4) New targets for 45nm and 32nm deployment such as stress/strain modeling, layout support for double-patterning lithography, and 'design for equipment' synergies.

Essential Issues in Analytical Placement Algorithms

“…Therefore, it is desirable to develop placement techniques that can spread blocks/cells over the whole placement region to lower the chip temperature variation. Kahng, et al proposed an analytical placement algorithm to minimize the maximum temperature and improve the chip reliability 28) . In addition to the maximum temperature, the distribution of hot blocks/cells and thermal gradient are also important and should be considered to reduce the on-chip performance variations.…”

Design methodologies, frameworks and implementations on reconfigurable devices for timing and energy optimizations

“…One important thermal effect is the induced degradation in metal interconnects, a phenomenon called Electromigration [ 123,20,88], which impacts the life-span of a chip and increases the failure probability rate. Moreover, the increased junction temperature affects the transistor threshold voltage, carrier mobility and wire resistivity which translate to performance degradation in many cases [62]. Last but not least, junction temperature results in the exponential increase of leakage power.…”