Essential Issues in Analytical Placement Algorithms

Abstract

The placement problem is to place objects into a fixed die such that no objects overlap with each other and some cost metric (e.g., wirelength) is optimized. Placement is a major step in physical design that has been studied for several decades. Although it is a classical problem, many modern design challenges have reshaped this problem. As a result, the placement problem has attracted much attention recently, and many new algorithms have been developed to handle the emerging design challenges. Modern placement algorithms can be classified into three major categories: simulated annealing, min-cut, and analytical algorithms. According to the recent literature, analytical algorithms typically achieve the best placement quality for large-scale circuit designs. In this paper, therefore, we shall give a systematic and comprehensive survey on the essential issues in analytical placement. This survey starts by dissecting the basic structure of analytical placement. Then, various techniques applied as components of popular analytical placers are studied, and two leading placers are exemplified to show the composition of these techniques into a complete placer. Finally, we point out some research directions for future analytical placement.

Layout driven FPGA packing algorithm for performance optimization

“…We choose the analytical placement [6] engine for our pre-packing placement for its shorter runtime and better quality. Since the netlist after fixed packing is a mixture of logic elements and clusters, a multi-density optimization method is proposed in our analytical placement.…”

A proximal alternating direction method of multipliers for a minimization problem with nonconvex constraints

“…All the proposed models try to minimize the wire-length subject to no cell overlaps. Among these models, the density control half-perimeter wire length (HPWL) model is common in analytical placement, see Chang et al [12].…”

A scaled LSE wirelength model for VLSI global placement

“…The methods of these placers can be grouped into three classes: simulated annealing based methods [3], [4], partition-based placement methods [5]- [7], and analytical approaches [8]- [17]. Currently the analytical approaches are main approaches for the VLSI placement problem [18].…”

“…The produced global placement results are further improved by the phases of legalization and detailed placement. In the analytical approaches, the global placement phase is considered as the most important step, since it has great impact on the overall placement quality [18].…”

“…The popular smooth wirelength approximations are as follows: the logsum-exponential (LSE) wirelength model [9], the quadratic wirelength model [10], the L p -norm wirelength wirelength model [14], and the CHKS wirelength wirelength model [19]. A detailed comparison of these models can be found in [18].…”