--As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult. With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels. Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.In this paper a new em pirical gate delay m odel is proposed.Instead of building the em pirical equations in term s of capacitance loading and input-signal transition tim e, the m odels are generated in term s of param eters which com bine the benefits of em pirically derived k -factor m odels and switch-resistor m odels to efficiently: 1) handle capacitance shielding due to m etal interconnect resistance, 2) m odel the RC interconnect delay, and 3) provide tighter bounds for sim ultaneous switching.
Recenily, seveml design auiomaiion approaches for delay and skew minimization of clock nets have been proposed. These approaches are based upon varying the widths and lengths of the clock tree wires io minimize skew and sometimes delay. Most of these iechniques do noi consider the clock iree power dissipation, occupied area, or the reliabiliiy of ihe resvlts with regard to the ineviiable process variations. In this paper, concurreni buffer insertion and global wire width adjusimenis are used to reliably reduce both delay and power from that obtained for a reliable buflerless soluiion. Moreover, in spite of ihe belief ihai ihe mismaich in bufler delays can resuli in significant clock skew, our resulis show ihai buflers can actually reduce the process dependent skew for a reliable design.
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied to estimation of the timing yield. Key features of these models are that they are easy to compute, they include a powerful model of withindie correlation, and they are "full-chip" models in the sense that they can be applied with ease to circuits with millions of components. As such, these models provide a way to do statistical timing analysis without the need for detailed statistical analysis of every path in the design.
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