A gate-delay model for high-speed CMOS circuits

Abstract

--As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult. With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels. Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.In this paper a new em pirical gate delay m odel is proposed.Instead of building the em pirical equations in term s of capacitance loading and input-signal transition tim e, the m odels are generated in term s of param eters which com bine the benefits of em pirically derived k -factor m odels and switch-resistor m odels to efficiently: 1) handle capacitance shielding due to m etal interconnect resistance, 2) m odel the RC interconnect delay, and 3) provide tighter bounds for sim ultaneous switching.

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

“…Unlike most timing analyzers, we precharacterize the 10-50% transition time to model the effective capacitance loading. We use the "effective capacitance" model presented in [12,13] to obtain an accurate estimate of the gate output waveform for highly-resistive interconnect loads. The second-order driving point admittance of the load, which is modeled by a π-circuit, is shown to be adequately accurate for on-chip RC interconnect.…”

“…Essentially, the π-load is mapped to an effective capacitance, C eff , which is then used to iteratively compute the parameters of a single-resistor voltage-ramp model ( Fig. 1) [13]. This model, with the π-load, gives the necessary gate output waveform.…”

“…(12) The sensitivities of the π-circuit parameters, R, C 2 , C 1 , with respect to w l are readily calculated. Even though C eff has no closed-form solution, the partials ∂C eff /∂R, ∂C eff /∂C 2 , ∂C eff /∂C 1 are computed from the last iterative solution of C eff [12,13].…”

“…The effect of sizing a component in stage n on the delay of stage n, , is calculated from single-stage delay sensitivity equations, (10) - (13). The effect of sizing a component in stage n on any other stage along the path is captured by the following two observations:…”

Software Implementation of Break-Up Algorithm for Logic Minimization

“…Implementation of Logic Switching circuit has two types: Two-level synthesis and multilevel synthesis [10]. Implementation of multilevel synthesis faces problems like propagation delay, errors and complexity in designing although it requires fewer gates and fewer connections compared to two level synthesis [11][12][13][14][15][16] …”