Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

Abstract

Abstract-The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap (available: http://public. itrs.net). Our work gives the first-ever quantification of the impact of model guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guardband reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90-and 65-nm libraries and technologies as well as an industrial embedded processor core implemented in 45 nm. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, in our open-source cores, on average we observe 13% standard-cell area reduction, 12% routed wirelength reduction, 13% dynamic power reduction and 19% leakage power reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. For the embedded processor core we observe up to 8% standard-cell area reduction, 7% routed wirelength reduction, 5% dynamic power reduction, and 10% leakage power reduction at 30% guardband reduction. We also report a set of fine-grain SPICE simulations that accurately assesses the impact of process guardband reduction, as distinguished from overall guardband reductions, on yield. We observe up to 4% increase in number of good dies per wafer at 27% process guardband reduction (i.e., with fixed voltage and temperature). Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.Index Terms-Design guardband, design of experiments, process variation, yield.

New Logic Synthesis as Nanotechnology Enabler

“…Solutions different than circuit overdesign [69] exist for the variability problem. One example is to construct computing machines purposely exposing hardware variations to various layers of the system stack, including software [70].…”

Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation

“…The number of gross dies on a wafer corresponding to a u% guard-band reduction is given by Equation ( 11), where l is the radius of the wafer and V u% is the die area corresponding to a u% guard-band reduction [Jeong et al 2009]; the second term in the equation accounts for wasted area around the edges of the circular wafer. The die area V u% is given by Equation ( 12), where n pe and n cgu are the number of processing elements and clock-generation units, respectively; V pe , V noc , and V cgu are the area of a processing element, the interconnect, and the clock generation unit, respectively; and v sc ∈ [0, 1] is the fraction of the scaled logic.…”

“…This is illustrated in Figure 1(a). However, worst-case design results in a considerable increase in circuit area and power consumption [Jeong et al 2009], reducing the benefits of technology scaling. This work deals with the design of real-time systems for streaming applications constrained by a throughput requirement with reduced design margins, referred to as better-than-worst-case design.…”