Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Abstract

Gate-all around (GAA) device is one of the cutting-edge technologies and the advantages of these devices can be improved by incorporating the dual material (DM) and graded channel (GC) techniques. This manuscript investigates for the first time, the performance analysis of DMGC CGAA FET and circuit applications such as inverter, NAND, NOR, ring oscillator and 6T SRAM. It has been found that the Ioff, SS, DIBL, Ion/Ioff ratio are enhanced by an amount of 96.93%, 19.49%, 51.26%, 96.98% respectively for DMGC CGAA FET when compared to SMGC CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93%, 11.25%, and 10.07% respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7% with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

“…Moreover, the proposed DMGC CGAA FET generates the stronger electric field at the interface of both the channel regions which results into enhanced carrier drift velocity and current driving capability. 32 Figure 3c represents the energy band diagram of both SMGC, and DMGC and observed that barrier height of the DMGC is greater compared to SMGC which indicates that the DMGC is more immune to SCEs. Since, an enhanced performance is noticed with DMGC CGAA FET, the further analysis in this manuscript is focused to explore the temperature, SHE, and linearity performance investigation of DMGC CGAA FET.…”

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

“…Additionally, this cylindrical shape allows for better control over the flow of electrons through the channel, leading to improved transistor performance, reduced leakage current, and enhanced energy efficiency. Further, gate engineering and channel engineering are the two primary techniques used to improve the electrostatic integrity of the CGAA FET [17,18]. The dual material (DM) gate is one of the gate engineering techniques which minimizes the SCEs by maintaining the higher work function at source end than the drain end and this lower work function at drain end reduces the DIBL effect.…”

Design Considerations into Circuit Applications for Structurally Optimised FinFET

“…The fundamental components of SoC IC design include simple digital/analog circuits including CMOS logic gates, operational amplifiers, current mirrors, SRAM cells, etc. [1][2][3] With the advancement of technology and improved economy, the demand for these portable devices has increased greatly. According to the most recent reliable statistics and projections, the revenue of consumer electronics products is anticipated to reach US $450,387 Million in 2024.…”