Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

High-Current GaSb/InAs(Sb) Nanowire Tunnel Field-Effect Transistors

“…T HE rapid development of semiconductor technology during the last few decades has resulted in high-performance transistors in both Si and III-V semiconductor technologies [1], [2]. However, MOSFETs suffer from a fundamental lower limit of 60 mV/decade subthreshold swing (SS) at room temperature, and a corresponding lower limit of the power dissipation at a given threshold voltage and on-current level.…”

Link between Gas Phase Reaction Chemistry and the Electronic Conductivity of Atomic Layer Deposited Titanium Oxide Thin Films

“…Atomic layer deposition (ALD) is a cyclic form of chemical vapor deposition enabling growth of highly uniform and conformal thin films over complex surface topologies for many applications including electronics and energy technologies. For example, ALD has become an indispensable tool in nanoelectronics to form the gate dielectric layers at the heart of metal oxide semiconductor field effect transistors. , The availability of a large range of molecular precursors enables development of ALD processes for deposition of a wide array of metal oxides, nitrides, phosphides, sulfides, carbides, and an increasing number of elemental metals. ALD has become increasingly important in corrosion protection, , synthesis of catalysts, , battery electrode coatings, − and in surface passivation of solar cells. − …”

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

“…Fig. 8 shows some recently reported I on /I off ration in different structures including bulk planar, SOI, and multi-gate, MOS transistors for the technology node in the range of 45 to 22 nm [25][26][27][28][29][30][31][32][33]. In principle, I on /I off ratio degrades as the supply voltage reduces.…”

“…Many device structures which demonstrate better performances or scalability have been reported. Physically, even better device structures [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] have been proposed and many feasible fabrication techniques have been developed. In the FinFET or tri-gate structure, the current flows on the three surface regions and that provides even better electrostatic control.…”