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In this letter, we demonstrate that negative bias temperature instability of high-k (HfO 2 /SiO 2 ) gate dielectric stacks can be greatly improved by incorporating fluorine and engineering its concentration depth profile with respect to HfO 2 /SiO 2 interface. It was found that fluorine is easily incorporated in HfO 2 /SiO 2 at low temperatures (≤ 400 • C) by F 2 anneal in the presence of UV radiation. Fluorine tends to segregate at the HfO 2 /SiO 2 interface and, to a lesser extent, diffuses into the underlying SiO 2 /Si interface. The HfO 2 /SiO 2 stacks with F addition show significantly reduced (<50%) positive charge trapping and interface states generation compared to control samples without F.Index Terms-Fluorine, HfO 2 /SiO 2 , high-k, interface states, negative bias temperature instability (NBTI), positive charges.

The authors report on the chemical bonding structure of the HfO2∕Si (001) stack after the SiO2 interfacial layer (IL) is partially removed by a reactive titanium metal overlayer. Using synchrotron photoelectron spectroscopy, they found that ultrathin SiO2-like IL ∼6.5Å thick, which is significantly less than the initial SiO2 IL thickness of ∼15Å, exists at the HfO2∕Si interface with an overlying Ti electrode. The dissociated Si from SiO2 IL is believed to go onto Si substrate where it regrows epitaxially. The interfacial trap density of the Ti-electrode sample was extracted to be ∼1.6×1011eV−1cm−2 near the midgap of Si, which was comparable to that of the control sample with W electrode.

We report the chemical bonding structure and valence band alignment at the HfO2∕Ge(001) interface by systematically probing various core level spectra as well as valence band spectra using soft x rays at the Stanford Synchrotron Radiation Laboratory. We investigated the chemical bonding changes as a function of depth through the dielectric stack by taking a series of synchrotron photoemission spectra as we etched through the HfO2 film using a dilute hydrogen fluoride solution. We found that a very nonstoichiometric GeOx layer exists at the HfO2∕Ge interface. The valence band spectra near the Fermi level in each different film structure were carefully analyzed, and as a result, the valence band offset between Ge and GeOx was determined to be ΔEv (Ge–GeOx)=2.2±0.15eV, and that between Ge and HfO2, ΔEv (Ge–HfO2)=2.7±0.15eV.

In this letter, we demonstrate that formation of a Zr-silicate interfacial layer between ZrO2 and Si substrate can be controlled by the solid state reaction between Zr and an underlying SiO2/Si substrate through in situ vacuum anneals and subsequent UV oxidation. By investigating the chemical shifts of Si2p, Zr3d, and O1s features using x-ray photoelectron spectroscopy, the formation of a Zr-silicide phase after in situ vacuum anneals of the Zr/chemical SiO2/Si gate stack at 200 °C was confirmed. The Zr-silicide was oxidized to form a Zr-silicate phase in the subsequent UV-ozone oxidation treatment. According to spectroscopic analyses, Zr-silicate bonding occurred in the interfacial layer for the in situ vacuum annealed samples. Vacuum annealed samples containing the silicate interface layer exhibited excellent dielectric characteristics, such as negligible capacitance–voltage hysteresis (∼10mV), lower fixed charge density, and reduced equivalent oxide thickness compared to unannealed samples.

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We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of I eff (N/P) = 621/453 μA/μm at I off = 10 nA/µm at V DD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies. IntroductionFinFET has become a viable technology for 22nm node and beyond [1][2][3][4]. Bulk FinFET [1-3] requires punchthrough stop (PTS) doping below the fin channel to suppress short-channel effects (Fig. 1a). This PTS results in undesirable device variability. Dielectric-isolated FinFET (DI-FinFET) eliminates the need of PTS doping, and thus avoids its adverse impact (Fig. 1b). Using SOI substrates is the most straightforward way to fabricate DI-FinFETs. However, bulk substrates can offer some integration and device design flexibility. To combine the advantages of SOI FinFETs and the flexibility to use bulk substrates, motivation exists to fabricate SOI-like FinFETs on bulk substrates. This has indeed been demonstrated in the original FinFET work [5] by thermal oxidation of fin bottom. Nevertheless, this early approach has a major manufacturing issue -fins tend to tilt due to oxidation induced stress. In this paper we report a novel DI-FinFET approach, Bottom Oxidation Through STI (BOTS), to solve critical manufacturing and device issues of DI-finFET. The extendibility of BOTS to future CMOS technologies is also demonstrated. Bottom Oxidation Through STI (BOTS) Process FlowThe BOTS process flow for fabricating SOI fins on bulk substrates is depicted in Fig. 2. SOI fins are formed by converting the bottom portion of bulk fins into a buried oxide layer (BOX) through thermal oxidation. A novel feature of BOTS is the use of STI oxide for two purposes. First, STI surrounding fins acts as a mechanical anchor to hold the fins straight during oxidation. Second, STI regions are filled with permeable oxide, allowing oxidation species to diffuse through STI to oxidize the fin bottom. The top portions of the fins are covered by nitride spacers and nitride caps and they become SOI fins after oxidation. Vertically standing SOI fins with a pitch of 42nm are achieved by BOTS (Fig. 3). In contrast, conventional oxidation without STI [5] results in tilted fins (Fig. 4). Excessive oxidation stress may generate defects in SOI fins. To minimize oxidation stress, the bottom portions of fins are further recessed and intentionally narrowed prior to oxidation. As a result, only a small amount of oxidation is needed to laterally oxidize the narrow fin bottom from both sides (F...