2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers 2014
DOI: 10.1109/vlsit.2014.6894390
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Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

Abstract: We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of I eff (N/P) = 621/453 μA/μm at I off = 10 nA/µm at V DD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region,… Show more

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Cited by 16 publications
(11 citation statements)
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“…Figure 2 shows the geometry of GAA CNTFET modeled by Silvaco's ATLAS 3D tool, which uses a single CNT as a channel with gate wrapped around the channel to provide complete control over the flow of charge carriers through the channel as ballistic transport. The High_K gate dielectric materials have been used in CMOS process and FinFETs [24][25][26], the same concept of equivalent oxide thickness is used here to overcome gate tunneling which causes leakage through the dielectric layer and palladium as gate and source/drain contact materials due to its better wettability and compatibility with other material layers in the CNTFET device structure [13,27]. The palladium as conductor for source/drain/gate contacts, heavily doped source/drain n +regions with donor concentration of 1e+20 /cm 3 for ohmic contacts and SiO 2 -HfO 2 stack as gate dielectric material to provide better gate coupling without increase in gate tunneling current for optimum device performance and leakage reduction has been used to model and simulate GAA CNTFET for robust applications.…”
Section: Simulation and Estimation Of Band Gap And Density Of States mentioning
confidence: 99%
“…Figure 2 shows the geometry of GAA CNTFET modeled by Silvaco's ATLAS 3D tool, which uses a single CNT as a channel with gate wrapped around the channel to provide complete control over the flow of charge carriers through the channel as ballistic transport. The High_K gate dielectric materials have been used in CMOS process and FinFETs [24][25][26], the same concept of equivalent oxide thickness is used here to overcome gate tunneling which causes leakage through the dielectric layer and palladium as gate and source/drain contact materials due to its better wettability and compatibility with other material layers in the CNTFET device structure [13,27]. The palladium as conductor for source/drain/gate contacts, heavily doped source/drain n +regions with donor concentration of 1e+20 /cm 3 for ohmic contacts and SiO 2 -HfO 2 stack as gate dielectric material to provide better gate coupling without increase in gate tunneling current for optimum device performance and leakage reduction has been used to model and simulate GAA CNTFET for robust applications.…”
Section: Simulation and Estimation Of Band Gap And Density Of States mentioning
confidence: 99%
“…Researchers have been extensively studying more cost effective alternatives to SOI wafers by creating dielectrically isolated wafers through various integration schemes. Non-planar transistors such as fin channel field effect transistor (finFET) are better suited to dielectrically isolated technology since it is easier to achieve dielectric isolation through thermal processes in the fins than in planar transistors 12 . However, finFET technology carries its own manufacturing challenges.…”
Section: Channel and Gate Engineeringmentioning
confidence: 99%
“…In next step (step-II), the fin surface is lightly oxidized by the high-pressure oxygen plasma in the chamber, forming a thin layer of oxide (1∼2 nm) on the etched Si surface to protect the fabricated Si fin in next etch-step. It is the critical step of the unique process approach, which removes the protective layer of nitride spacers for the formation of notches reported in reference 6 and simplifies the whole process. Subsequently, an isotropic etch by Cl 2 plasma is performed to form a pair of notches in the middle of both fin sidewalls (step-III).…”
Section: Device Fabricationmentioning
confidence: 99%
“…6 For the first time, this letter reports a novel approach to fabricate a Fin-OnOxide (FOO) FinFET on the Si substrate with a small modification on normal bulk-Si FinFET integration process. The fabricated FOO FinFETs with L G of 27 nm and 14 nm demonstrated improved SCE immunity compared with the bulk-Si FinFET counterpart due to the physically isolated channel.…”
mentioning
confidence: 99%