Scaling Challenges for Advanced CMOS Devices

Abstract

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

“…Figure 10 shows a schematic view of the step. This step is critical for two reasons: first, it protects the epi S/D (S/D refers to the epitaxially deposited transistor source and drain) region during the nanowire release step 14 and, second, it suppresses parasitic capacitance between the S/D and gate. 15 Figure 10 shows a schematic view of the step.…”

“…IMEC, among others, has proposed complimentary stacked GAA, vertical GAA, TFET, and 2D FET's (utilizing graphene or dichalcogenides). 14 In this example, we will take a closer look at the vertical GAA device. In theory, a vertical GAA device with a Si nanowire has all of the electrostatic benefits of a horizontal GAA device, but its gate length is not restricted by its "footprint" on the wafer.…”

The Challenges of Advanced CMOS Process from 2D to 3D

“…In the most cases, the fins at the edges of a cluster suffer a higher variability than those in the middle. To achieve uniform fin width and height in a cluster, dummy fins are required [27]. Some dummy fins need to be cut at the pitch.…”

“…Furthermore, the dry etching of fins is more stringent due to the 3D topography, therefore, a plasma pulsing scheme may be viable for minimizing Si loss [25]. The growth of defect-free alternated fin materials for high mobility channel application is also a challenge due to differences in thermal budget and lattice matching [27].…”

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

“…However there may be tradeoff between the various optimization measures for a particular application. In the nanoscale device, with the scaling of channel length, the device behavior also departs from its usual characteristics and short channel effects comes into play [2]. The device channel mobility becomes field dependent with increase in electric field which results in velocity saturation.…”