Directed self-assembly (DSA), an emerging lithographic technique, has attracted increasing attention as a result of its advantages of low cost, high throughput and convenient processing.

We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Based on the PR consume model, we are able to prove the process efficiency and low cost of SDS. We also show that SDS can improve the integration for higher bit density. Finally, we find that the critical dimension (CD) of stair divided zone shifts post stair etching. We investigate the reason and point out that, it is necessary to make compensation in layout to ensure the precise alignment of stairs.

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In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins. It is due to formation of quasi-surrounding gate electrodes on scalloping fins by a special Si etch process. The entire integration flow of the S-FinFETs is fully compatible with the mainstream all-last HKMG FinFET process, except for a modified fin etch process. The drain-induced barrier lowering and subthreshold swing of the fabricated p-type S-FinFETs with a 14-nm physical gate length are 62 mV/V and 75 mV/dec, respectively, which are much better than those of normal FinFETs with a similar process. With an improved short-channel-effect immunity in the channels due to structure modification, the novel structure provides one of possibilities to extend the FinFET scalability to sub-10-nm nodes with little additional process cost.

The paper proposed a simple and novel approach to fabricate Fin-On-Oxide (FOO) FinFETs on silicon (Si) substrates for improved electrical characteristics in scaled devices. Based on conventional bulk-Si FinFET integration flow, a special step of a fin notch etching is performed, followed by a process of liner oxidation and isolation-oxide filling and recess. The fin above the notch is physically isolated from the substrate and turns into a self-aligned FOO structure. The fabricated p-type FOO FinFETs have demonstrated excellent short-channel effect (SCE) characteristics with subthreshold slope (SS) of 69 mV/dec and drain-induced barrier lowering (DIBL) of 22 mV/V for a physical gate length (L G ) of 27 nm. For 14 nm devices, SS of 86 mV/dec and DIBL of 106 mV/V have been achieved, which are much better than those of the bulk-silicon FinFET counterpart with similar process. Meanwhile, the steady threshold voltage (V TH ) shifting by the substrate biasing is realized in the FOO FinFET without performance degradations. The linearity of the V TH on the bias voltage is −6 mV/V. The self-aligned FOO-FinFET with a simple process provides a promising method to improve the SCE immunity as well as provides the multi-V TH operation for the scaled FinFET on Si substrates for future ultra-low power circuit applications. With more than 10 years of continuous research and development, bulk-silicon (Si) FinFET has been commonly recognized as one of the most promising device architectures for the mass production of the most advanced CMOS integration circuits.1,2 Due to the multi-gates, such as the double or the triple gates on a narrow fin channel, FinFET has a well-controlled electrostatic integrity in the short channel even with the physical gate length (L G ) below 30 nm. However, the actual fin channel in the normal bulk-Si FinFET is within the fin body tied to the Si substrate. This requires a careful design of punch-through stopper (PTS) doping to suppress the sub-channel leakage current at the bottom of the fin.3,4 The PTS doping also causes carrier mobility degradations and serious threshold voltage (V TH ) variability in transistors.5 Different from the bulk-Si FinFET, a FinFET fabricated on the SOI substrate (SOI FinFET) has an isolated fin channel naturally formed by the buried oxide. SOI FinFET has the advantages of simplified integration process, reduced leakage and improved device variability. However, it suffers from a high-cost starting wafer and a series of process issues for integrating the high-voltage or the passive components on SOI substrates. As L G continuously scaling down, the short channel effect (SCE) and the channel substrate leakage in the transistor become more serious. The FinFETs with the physical isolation fin channels on conventional Si substrates become one of the most interesting research topics for scaling FinFETs technology in the future.Some papers reported the fabrication process of the advanced isolated structure on Si substrates with a complicated process. 6 For the first time, this let...

In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the polysilicon gate etch based on the composite SiO 2 ∕Si 3 N 4 ∕SiO 2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO 2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α-Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low V T . Compared with halo doping with the same V T,sat at V DD = 0.8 V, despite no I ON enhancement, the SPW reduces DIBL by 45% and enhances I EFF by 18%. Compared with halo doping with the same I OFF = 100 nA/µm at V DD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances I ON by 5%, and improves I EFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) Manuscript leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping.Index Terms-Band-to-band tunneling (BTBT), drain-induced barrier lowering (DIBL), ground plane (GP), halo, pocket, short-channel effect (SCE). tion.

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