Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs

Qin, Changliang; Yin, Huaxiang; Wang, Guilei; Hong, Peizhen; Ma, Xiaolong; Cui, Hushan; Lu, Yihong; Meng, Lingkuan; Yin, Haizhou; Zhong, Huicai; Jiang, Yan; Zhu, Huilong; Xu, Qing; Li, Junfeng; Zhao, Chao; Radamson, Henry H.

doi:10.1016/j.mee.2017.07.001

Cited by 12 publications

(8 citation statements)

References 22 publications

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“…While anisotropic wet etching is the traditional fabrication technique for cavities in microelectromechanical systems (MEMS) [1] (Fig. 1a), further applications include patterned sapphire substrates for gallium nitride-based light emitting diodes [2] and source-drain engineering for metaloxide-semiconductor field-effect transistors (MOSFETs) on the nanoscale [3], [4]. A similar fabrication process is epitaxial growth of Si or silicon-germanium (SiGe) on non-planar substrates (Fig.…”

Section: Introductionmentioning

confidence: 99%

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

et al. 2020

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We present numerical methods to enable accurate and robust level-set based simulation of anisotropic wet etching and non-planar epitaxy for semiconductor fabrication. These fabrication techniques are characterized by highly crystal orientation-dependent etch/growth rates, which lead to non-convex Hamiltonians in their description by the level-set equation. As a consequence, instable surface propagation may emerge, leading to unphysical results. We propose a calibration-free Stencil Lax-Friedrichs scheme and an advanced adaptive time-stepping approach, tailored to the level-set speed functions associated with anisotropic etching and epitaxy. The scheme calculates the numerical dissipation based on information about the local geometry and the nature of the etch rates/growth function, which enables an optimized tradeoff between overly rounding of sharp geometric features and stable surface propagation. Furthermore, we introduce the deposition top layer method, which allows for robust handling of multiple material regions in non-planar epitaxy simulations. Both methods are demonstrated in a prototypical implementation, which is used to validate the capability and accuracy of our approaches. In particular, two-dimensional wet etching and three-dimensional epitaxy simulations are performed and characteristic geometry parameters are compared to the ideally expected values, showing robustness and high accuracy.

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Section: Introductionmentioning

confidence: 99%

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

et al. 2020

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“…According to the result of strain simulation about advanced sigma-shape recessed structures, there are two key structure factors affect device's performance. One is the distance between the sigma-shape recess and its channel region; another is tip depth [13]. In simple U-shape recess structure, only the distance between the U-sharp recess and its channel region is significant in structure's influence.…”

Section: Resultsmentioning

confidence: 99%

Effects on selective epitaxial growth of strained-SiGe p-MOSFETs on various (001) Si recess structures

Hong

Perng

2017

J Theor Appl Phys

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Influences of source and drain recess structures on SiGe epitaxy growth, SiGe step height, facet formation, I D,sat and resistance performance are investigated. Growth rate of SiGe height increases with decreased recess width at a fixed depth of 62 nm. Under a fixed recess width of 96.3 nm, the deeper the recess, the higher the growth rate of SiGe height. An increase in the depth/width ratio of the recessed Si geometry may promote SiGe {001} growth. Upon the recess, SiGe step height is influenced by the initial SiGe orientation. A longer {001} facet of SiGe initial orientation causes a higher growth rate of SiGe step height. Higher I Dsat and lower resistance can be achieved by increasing SiGe volume with wider recess width, deeper recess depth, and higher SiGe step height.

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“…In order to induce more strain in the channel area, the original round shape of recess (or trenches) in S/D regions was changed to sigma (“∑”) shape in the 45-nm node. It is because that the SiGe layers could be placed closer to the channel area [ 93 , 94 ].…”

Section: Epitaxy Of Nano-scaled Transistorsmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs

Cited by 12 publications

References 22 publications

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

The Level-Set Method for Multi-Material Wet Etching and Non-Planar Selective Epitaxy

Effects on selective epitaxial growth of strained-SiGe p-MOSFETs on various (001) Si recess structures

State of the Art and Future Perspectives in Advanced CMOS Technology

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