Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices

Meng, Lingkuan; Hong, Peizhen; He, Xiaobin; Li, Chunlong; Li, Junjie; Li, Junfeng; Zhao, Chao; Wei, Yayi; Jiang, Yan

doi:10.1016/j.apsusc.2015.11.139

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…The key point of the approach is that a highly tuned etch selectivity of SiO 2 over α-Si material can be easily obtained from low to even infinitely high values by optimized process conditions, which has been revealed according to previous studies by us [32]. At the same time, we have reported α-Si material used as a robust capping layer that can generate successfully sub-30-nm gate patterns with smooth and perfectly vertical sidewalls for advanced 22-nm and 14-nm nodes CMOS devices, respectively [32, 33]. …”

Section: Introductionsupporting

confidence: 53%

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

Meng

Gao

et al. 2016

Nanoscale Res Lett

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A novel nanofabrication technique which can produce highly controlled silicon-based nanostructures in wafer scale has been proposed using a simple amorphous silicon (α-Si) material as an etch mask. SiO2 nanostructures directly fabricated can serve as nanotemplates to transfer into the underlying substrates such as silicon, germanium, transistor gate, or other dielectric materials to form electrically functional nanostructures and devices. In this paper, two typical silicon-based nanostructures such as nanoline and nanofin have been successfully fabricated by this technique, demonstrating excellent etch performance. In addition, silicon nanostructures fabricated above can be further trimmed to less than 10 nm by combing with assisted post-treatment methods. The novel nanofabrication technique will be expected a new emerging technology with low process complexity and good compatibility with existing silicon integrated circuit and is an important step towards the easy fabrication of a wide variety of nanoelectronics, biosensors, and optoelectronic devices.

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Section: Introductionsupporting

confidence: 53%

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

Meng

Gao

et al. 2016

Nanoscale Res Lett

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“…Some related work on pattern transfer was reported in our previously published paper regarding advanced CMOS devices. 47,48 Currently, a DSA-related study with no neutral layer is being carried out in different design layout trenches to achieve sub-20 nm features with a long-range order, and interesting results will be further published in following papers.…”

Section: Application Of New Ps-b-pc On Different Substratesmentioning

confidence: 99%

Study of the perpendicular self-assembly of a novel high-χ block copolymer without any neutral layer on a silicon substrate

et al. 2019

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“…In our previous studies, with E-beam lithography, we have successfully developed gate patterning techniques used to fabricate 22 nm planar device and 14 nm node FinFET devices by a novel α-Si capping layer combined with SiO 2 /Si 3 N 4 /SiO 2 multi-layer mask structure (α-Si/ONO). [8][9][10] As a further study, different from work presented previously, 193 nm lithography process is introduced to enable further scaling by a completely available α-C/ONO structure for IC industry. Gate length with sub-30 nm length can be achieved by a direct trimming process.…”

mentioning

confidence: 99%

“…In our previous study, it has been observed that, although no extra significant modification is carried out in gate mask stack, mask etch process window remains smaller to show a significant influence on the subsequent α-Si dummy gate etch. 10 In addition, many feature profiles that are tolerable at longer gate lengths, such as line edge roughness, footing, notch, and tapered profiles, are now extremely detrimental to transistor performance.…”

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confidence: 99%

Etch Mechanism Study in Gate Patterning for 14 nm Node and beyond FinFET Devices

Meng¹,

Jiang²

2017

ECS J. Solid State Sci. Technol.

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In this work, two particular and interesting phenomena encountered in 14 nm gate mask etch including severe α-Si dummy gate top surface recess and reversely tapered Si 3 N 4 mask profiles have been observed for the first time by using 193 nm lithography. Due to 3D topography of FinFET devices, the hard mask etch influences the final gate profile, notch formation and CD variation, which, in turn, impacts electrical performance and reliability of the devices. Therefore, fully understanding gate mask etch mechanism is a key to avoid device performance degradation. It is believed that local differential charging between the sidewall surface and feature bottom is responsible for the formation of etch failure associated with gate mask, because it induces deflected ions to cause enhanced ion etch behavior. We have proposed two simple process optimizations which not only can reduce dummy gate top surface recess but also help improve the anisotropy of gate mask etch. The patterning strategies presented in this paper are very useful and also offer a potentially universal method for the fabrication of advanced FinFET and various novel nanodevices in an efficient way.

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Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices

Cited by 6 publications

References 7 publications

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

Study of the perpendicular self-assembly of a novel high-χ block copolymer without any neutral layer on a silicon substrate

Etch Mechanism Study in Gate Patterning for 14 nm Node and beyond FinFET Devices

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