A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Seo, Kang-Ill; Haran, Bala; Gupta, Divya; Guo, Dechao; Standaert, T.; Xie, Ruiqing; Shang, Huiling; Alptekin, Emre; Bae, Dong-il; Bae, G.J.; Boye, Carol; Cai, Hao; Chanemougame, D.; Chao, Robin; Cheng, K.; Cho, J.; Choi, Kihyun; Hamieh, Bassem; Hong, Jong‐Ho; Hook, T.B.; Jang, Linus; Jung, Ju Young; Jung, Ranu; Lee, D.; Lherron, B.; Kambhampati, R.; Kim, B.; Kim, H.; Kim, K.; Kim, T. S.; Ko, Saebom; Lie, Fee Li; Liu, D.; Mallela, H.; Mclellan, Erin; Mehta, S.; Montanini, P.; Mottura, M.; Nam, Jong-Ho; Nam, S.M.; Nelson, Fan Z.; Ok, I.; Park, C.; Park, Y.; Paul, A.K.; Prindle, C.; Ramachandran, R.; Sankarapandian, M.; Sardesai, V.; Scholze, A.; Seo, Soon‐Cheon; Shearer, Jeffrey C.; Southwick, Richard G.; Sreenivasan, R.; Stieg, S.; Strane, J.; Sun, Xiao Wei; Sung, Min Gyu; Surisetty, C.; Tsutsui, Gen; Tripathi, Neeraj; Vega, Reinaldo A.; Waskiewicz, Christopher; Weybright, M.; Yeh, C.-C.; Bu, H.; Burns, Sean; Canaperi, D.; Celik, M.; Colburn, Matthew; Jagannathan, H.; Kanakasabaphthy, S.; Kleemeier, W.; Liebmann, Lars W.; McHerron, D.; Oldiges, P.; Paruchuri, Vamsi; Spooner, T.; Stathis, James H.; Divakaruni, R.; Gow, T. R.; Iacoponi, J.; Jenq, J.; Sampson, R.; Khare, Mukesh

doi:10.1109/vlsit.2014.6894342

Cited by 54 publications

(13 citation statements)

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“…4c we plot the iterative progresses of FinFETs as a function of time line. It is seen that, strikingly, the W fin has been levelling off since 2 decades 4,6,10,11,18,[22][23][24][25][26][27][28] . Our present work brings this nanostructure to a limit of 0.6 nm ML, an order of magnitude thinner than the W fin of state-of-the-art FinFETs.…”

Section: Discussionmentioning

confidence: 99%

“…After growth, the furnace was naturally cooled down to room temperature. [10] [28] Log (n) NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-020-15096-0 ARTICLE Semiconducting CNT and metallic CNT deposition. Semiconducting CNTs: the high-purity (>99.9%) semiconducting CNTs was mixed with toluene by a volume ratio of 1:15 and then ultrasonically treated for 10 min.…”

Section: Methodsmentioning

confidence: 99%

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A FinFET with one atomic layer channel

et al. 2020

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Since its invention in the 1960s, one of the most significant evolutions of metal-oxidesemiconductor field effect transistors (MOS-FETs) would be the three dimensionalized version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During the past decades, the width of fin (W fin ) in FinFETs has shrunk from about 150 nm to a few nanometers. However, W fin seems to have been levelling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting a template-growth method, different types of mono-layered two-dimensional crystals are isolated in a vertical manner. Based on this, FinFETs with one atomic layer fin are obtained, with on/off ratios reaching $10 7 . Our findings push the FinFET to the sub 1 nm fin-width limit, and may shed light on the next generation nanoelectronics for higher integration and lower power consumption.

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Section: Discussionmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

A FinFET with one atomic layer channel

et al. 2020

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“…Table 1 lists the main technology elements of 14 nm FDSOI along with a proposed 10 nm scenario. Gate and metal pitch numbers are based on competitive FinFET technologies [76]. Note that FDSOI technology did not use self-aligned contact (SAC) at 14 nm ground rules.…”

Section: Fdsoi Scalability and Global Landscapementioning

confidence: 99%

“…For 10 nm FDSOI, the gate length can remain the same as 14 nm node in view of unlikely scaling of the equivalent oxide thickness (EOT) of the gate dielectric. SAC needs to be adopted in the same manner as that FinFET technology is implemented [57,58,76] to accommodate the CPP scaling. Although FDSOI can use the popular replacement metal gate (gate-last) similar to FinFET, we believe a gate-first process with tungsten metal gate [77] with an insulator cap is easier to implement.…”

Section: Fdsoi Scalability and Global Landscapementioning

confidence: 99%

Fully depleted SOI (FDSOI) technology

Cheng¹,

Khakifirooz

2016

Sci. China Inf. Sci.

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“…3 and cell size is also fixed as previously reported [4] where HC cell is 0.053-Pm 2 and HD cell is 0.043-Pm 2 as testbed for exploring purpose. Actually, a couple of SRAM layout can be considered.…”

Section: Layout Artworkmentioning

confidence: 99%

SRAM cell performance analysis beyond 10-nm FinFET technology

Ichihashi

Woo

Parihar

2016

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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This paper describes the performance analysis of SRAM cell capability beyond 10-nm FinFET technology. Through the circuit simulation with a pseudo memory macro, optimized SRAM cell can demonstrate almost the same performance of traditional metal architecture though the read-out delay analysis. Comparing between HD (High-Density) and HC (High-Current) cell, HD cell shows better performance in the large array macro due to the less parasitic resistance and capacitance.

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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Cited by 54 publications

References 0 publications

A FinFET with one atomic layer channel

A FinFET with one atomic layer channel

Fully depleted SOI (FDSOI) technology

SRAM cell performance analysis beyond 10-nm FinFET technology

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