Fully depleted SOI (FDSOI) technology

Cheng, K.; Khakifirooz, A.

doi:10.1007/s11432-016-5561-5

Cited by 56 publications

(21 citation statements)

References 62 publications

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“…However, the electrical stability, especially bias stability under illumination evaluated mainly by threshold voltage shifts turns out to be a great concern [7][8][9]. It is found that a-IGZO TFTs with dual-gate (DG) driving not only improve device stability significantly, but also gain higher drain current and sharper subthreshold slope while maintaining low off-state current, which is superior to the single-gate (SG) driving devices [10][11][12][13][14][15][16]. So far, a few studies on DC and stability performance of DG a-IGZO TFTs have been made using empirical models of MOSFETs [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Cai

Yao

2017

Sci. China Inf. Sci.

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Based on the drift-diffusion theory, a simple threshold voltage and drain current model for symmetric dual-gate (DG) amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is developed. In the subthreshold region, most of the free electrons are captured by trap states in the bandgap of a-IGZO, thus the ionized trap states are the main contributor to the diffusion component of device drain current. Whereas in the above-threshold region, most of the trap states are ionized, and free electrons increase dramatically with gate voltage, which in turn become the main source of the drift component of device drain current. Therefore, threshold voltage of DG a-IGZO TFTs is defined as the gate voltage where the diffusion component of drain current equals the drift one, which can be determined with physical parameters of a-IGZO. The developed threshold voltage model is proved to be consistent with trap-limited conduction mechanism prevailing in a-IGZO, with the effect of drain bias being also taken into account. The gate overdrive voltage-dependent mobility is well modeled by the derived threshold voltage, and comparisons of the obtained drain current with experiment data show good verification of our model. Keywords amorphous InGaZnO, drift-diffusion current, dual-gate, thin film transistors, threshold voltage Citation Cai M X, Yao R H. A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors.

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Section: Introductionmentioning

confidence: 99%

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Cai

Yao

2017

Sci. China Inf. Sci.

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“…The physical structure of a planar junctionless transistor is shown in Figure 1a [11,21]. A PJLT is typically realized on a fully depleted silicon on insulator (FD-SOI) wafer [22], which is characterized by three layers: a handle substrate (silicon), an insulating layer often referred to as buried oxide or BOX since it is made of silicon dioxide and a thin silicon layer also known as device layer (silicon). In order to realize PJLT on FD-SOI wafers, the device layer is usually highly doped and characterized by a thickness in the range of tens to hundreds of nanometers.…”

Section: Physical Structure Of Pjltmentioning

confidence: 99%

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

et al. 2019

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In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

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“…Based on this example (Figure 12, left), the space in between the three vertical contacts can be CS.S.1, as N = 2. In this case, the third CS will get closer to CUA (Figure 12 spacers, an in situ doped epitaxy was performed to create raised source/drain (RSD) to reduce S/D resistance and contact resistance [35]. For this purpose, the rectangular contacts were drawn with dimensions of width = X and length = 2X (X2X), in which the length was along the transistor width, and contacts to Poly had a regular square shape of width = length = X (or slightly larger: X ~ 1.5X).…”

Section: Optical Proximity Correction For Contactsmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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Fully depleted SOI (FDSOI) technology

Abstract: Cu gettering to nanovoids in SOI materials Science in China Series E-Technological Sciences 46, 60 (2003); CO2 storage in depleted gas reservoirs: A study on the effect of residual gas saturation Petroleum 4, 95 (2018);. REVIEW .

Cited by 56 publications

References 62 publications

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

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