A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Cai, Minxi; Yao, Ruohe

doi:10.1007/s11432-016-9049-2

Cited by 8 publications

(5 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The double gate α-IGZO TFTs does not exhibit such variation of I OFF and SS. A similar observation was already made for DG a-IGZO TFTs [35], [34]. Table III gives the comparison of device simulation and electrical performance parameters with the coplanar structure of α-IGZO TFT.…”

Section: Device Simulationsupporting

confidence: 68%

See 1 more Smart Citation

Design of Double-Gate Tri-Active Layer Channel Based IGZO Thin-Film Transistor for Improved Performance of Ultra-Low-Power RFID Rectifier

Dargar

Srivastava

2020

IEEE Access

View full text Add to dashboard Cite

In a Radio Frequency Identification (RFID) circuit, the rectifier plays a vital role since it converts the received RF energy from a distant transmitter (reader) to power the entire RF circuit of the passive tag. The thin-film transistors have the potential to affect the rectifier circuit performance using the channel structural modification in the device to accomplish better gate-control for low-power operations. In this paper, the authors have presented a novel design of a double-gate amorphous In-Ga-Zn-O (IGZO) based thin-film transistor with a tri-active layer channel structure. Further, the experimental characterization of the device has been implemented using the SPICE model to analyze the device performance in the rectifier circuits. The simulation reports the competitive results with an improved rectifier performance using the proposed structure. The performance of ultra-low-power rectifier topologies has been compared with the conventional rectifier circuit. Among others, the differential rectifier circuit arrangement has a high power conversion efficiency of 20.06% for low input 0.45 V−0.61 V, whereas Self-V TH-Cancellation (SVC) configuration optimum power consumption is 0.14 μW. The promising results suggest the device deployment in the passive RFID tags and implantable devices in ultra-low-power integrated circuits.

show abstract

Section: Device Simulationsupporting

confidence: 68%

“…Our results have been compared with those obtained for DG α-IGZO TFTs. In particular, the magnitude of V TH shift is smaller, and SS and I OFF are increasing for V TG values greater than 0 V in the α-IGZO TFT [35], [36].…”

Section: Device Simulationmentioning

confidence: 94%

Design of Double-Gate Tri-Active Layer Channel Based IGZO Thin-Film Transistor for Improved Performance of Ultra-Low-Power RFID Rectifier

Dargar

Srivastava

2020

IEEE Access

View full text Add to dashboard Cite

show abstract

“…The channel length (L) and the channel width (W) are 20 and 100 µm, respectively. Another dimension indicated in the figure is the [8,9] was simulated to obtain its I-V curves and compare simulated with measured. Details about how we reproduced the experimental curve of the device by simulation were reported in [7].…”

Section: Introductionmentioning

confidence: 99%

Analytical I–V and C–V models for symmetric double-gate AOSTFTs

Hernandez-Barrios¹,

Estrada²,

Pashkovich³

et al. 2021

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this article we present a full physical analytical model (FAM) for symmetric double-gate amorphous oxide semiconductor TFTs (DG AOSTFTs). The current-voltage (I-V) model is physically described for the above-threshold operation regime. In this case, the general expression for the field effect mobility is evaluated for the potential at the centre of the semiconductor layer at V G = 1 + V T , obtaining the value of the mobility parameter called µ 1DG for DG-AOSTFT. This parameter can now be used to represent the field effect mobility expression like in the model known as the unified model and extraction method, which is widely used for modelling amorphous devices. The proposed FAM model contains the analytical capacitances-voltage (C-V) model and considers the specific characteristics of DG structures, including the potential different from zero, at the centre of the semiconductor layer. The model was described in Verilog-A for introducing in Silvaco's SmartSpice simulation program and was validated with simulated data and experimental characteristics of reported DG amorphous indium-galium-zinc oxide devices.

show abstract

“…Tsuji et al [14] developed an efficient model for numerical simulations of single-gate InGaZnO TFTs. Cai et al [15] successfully developed a drain current-voltage model for dual-gate InGaZnO TFTs, which is suitable for sub-threshold and above-threshold operating regions. However, the presented model is strongly dependent on the predetermined threshold voltage, which is also difficult to calculate from physical parameters.…”

Section: Introductionmentioning

confidence: 99%

Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates*

He¹,

Deng²,

Qin³

et al. 2020

Chinese Phys. B

View full text Add to dashboard Cite

An analytical drain current model on the basis of the surface potential is proposed for indium–gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) with an independent dual-gate (IDG) structure. For a unified expression of carriers’ distribution for the sub-threshold region and the conduction region, the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation, and to derive the potential distribution of the active layer. In addition, the regional integration approach is used to develop a compact analytical current–voltage model. Although only two fitting parameters are required, a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD. The proposed current–voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.

show abstract

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Cited by 8 publications

References 37 publications

Design of Double-Gate Tri-Active Layer Channel Based IGZO Thin-Film Transistor for Improved Performance of Ultra-Low-Power RFID Rectifier

Design of Double-Gate Tri-Active Layer Channel Based IGZO Thin-Film Transistor for Improved Performance of Ultra-Low-Power RFID Rectifier

Analytical I–V and C–V models for symmetric double-gate AOSTFTs

Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates*

Contact Info

Product

Resources

About