Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.
In recent years wireless sensor networks (WSNs) have gained significant attention because of their implementation in many different fields. As the nodes in WSNs are typically battery-powered, their lifetime is mainly limited by the sensor nodes power consumption. A typical energy-saving solution consists in implementing wake-up receivers (WuRxs), which are responsible for the sensor node activation only when required. In this work an ultra-low power multivibrator-based WuRx concept is proposed. The WuRx is composed of several input-triggered multivibrators, which generate pulses of fixed duration. These pulses are compared to the input signal through logic gates, which are predefined according to the wake-up call. The sensor node is activated if the codes match. An implementation in TSMC-180nm CMOS process is proposed and simulated. The WuRx consumes 0.8µW when detecting a 6ms wake-up call signal, and 58.4pW when in idle mode.
In this article the subthreshold characteristics of an inverting single input CMOS Schmitt trigger circuit are analyzed. Analytical expressions for the low-to-high and high-to-low hysteresis transition voltages are determined. The analytical model provides physical insight into the circuit behavior. The derived expressions are linearly dependent on the supply voltage and the temperature, and logarithmically dependent on the dimensions of the transistors. Simulation results validated the proposed model, with a maximum error between the analytical and simulated transition points smaller than 14mV. An ASIC in AMS 0.35µm CMOS process has been fabricated to experimentally validate the derived expressions. The maximum error between the analytical and measured transition points is below 36mV.
In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors' geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS 0.35µm CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.INDEX TERMS CMOS, hysteresis, low voltage, Schmitt trigger, subthreshold.
This article analyzes the operation of a low power inverting CMOS Schmitt trigger in weak inversion. The analysis is based on an earlier proposed analytical model, which relates the hysteresis voltages to the transistors' dimensions, the supply voltage, and the temperature. The maximum error between the analytical and simulated transition voltages is below 10%, relative to the supply voltage. By optimizing the device sizes, the error reduces to 4%. The operation of the Schmitt trigger in weak inversion is also experimentally validated through an ASIC fabricated in AMS 0.35μm CMOS process. The maximum error between the modeled and measured transition voltages is below 7%. Furthermore, the power consumption as a function of the supply voltage is analyzed. Overall, the proposed model may be used to optimize the operation of the analyzed Schmitt trigger circuit for low power operation.
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