SRAM cell performance analysis beyond 10-nm FinFET technology

Ichihashi, Motoi; Woo, Youngtag; Parihar, Sanjay

doi:10.1109/vlsi-tsa.2016.7480512

Cited by 3 publications

(2 citation statements)

References 5 publications

(4 reference statements)

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“…Hence, FinFET 6T-SRAM cells are no longer general purpose; they ar performance-, or power-centric. In the literature [85], three different FinF cells exist: high-density (HD), high-performance (HP), and high-current (H sistor sizing ratio for each of them is PU:AC:PD of 1:1:1, 1:1:2, and 1:2:2 for HC, respectively. Here, PU, AC, and PD represent pull-up, access, and pulltors, respectively.…”

Section: 𝑊 = 𝑛(2ℎ + 𝑡 𝑓𝑖𝑛 )mentioning

confidence: 99%

“…The ho margin (HSNM) is same in the HP and HC configurations because of the Hence, FinFET 6T-SRAM cells are no longer general purpose; they are either area-, performance-, or power-centric. In the literature [85], three different FinFET 6T-SRAM cells exist: high-density (HD), high-performance (HP), and high-current (HC). The transistor sizing ratio for each of them is PU:AC:PD of 1:1:1, 1:1:2, and 1:2:2 for HD, HP, and HC, respectively.…”

Section: 𝑊 = 𝑛(2ℎ + 𝑡 𝑓𝑖𝑛 )mentioning

confidence: 99%

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FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

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Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

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Section: 𝑊 = 𝑛(2ℎ + 𝑡 𝑓𝑖𝑛 )mentioning

confidence: 99%

Section: 𝑊 = 𝑛(2ℎ + 𝑡 𝑓𝑖𝑛 )mentioning

confidence: 99%

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

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Brain Inspired One Shot Learning Method for HD Computing

Nair

Purushothaman

2019

Communications in Computer and Information Science

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Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells

Perez

Mesalles

Villacorta

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

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FinFET technology is used in leading highperformance/power-efficient electronic products. This technology has proven its efficiency after 22nm technology nodes. However, FinFET technology has new manufacturing and design complexities. Thus, it is required to study the behavior of defects in FunFET-based SRAM memories, and developing new test strategies for those defects that are not covered by conventional test strategies based on CMOS fault modeling. This paper is oriented to open-gate defects hard-to-detect that are unique to FinFET based SRAM memory cells. The open-gate defect affects only one of the parallel fins of the driver transistors of the memory cell. The behavior of these defects is studied for the hold, read and write operations using realistic defect models. By using a shorter write time test, the detection of these defects is investigated. The effectiveness of the shorter write time test method at nominal parameters and under process variations is evaluated. The detection probability of these defects can be further enhanced using a higher power supply voltage.

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SRAM cell performance analysis beyond 10-nm FinFET technology

Cited by 3 publications

References 5 publications

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Brain Inspired One Shot Learning Method for HD Computing

Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells

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