Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short-channel effects

Mudidhe, Praveen Kumar; Nistala, Bheema Rao

doi:10.1007/s10825-022-01992-9

Cited by 5 publications

(7 citation statements)

References 42 publications

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“…The DIBL is better in DMGC than in SMGC because the DM creates a steplike potential in the channel, which lowers the peak electric field near the drain region and minimizes the drain influence. 12 Further the control gate with more work function controls the subthreshold behavior of the device thereby the DMGC results with reduced SS than its counterpart. Moreover, due to DM structure, the transport efficacy of the carriers enhances, causes an improvement in on-current depicted in Fig.…”

Section: T E O T T K39 1 High K Imentioning

confidence: 99%

“…The difference in work function provides the step like potential in the channel by which the drain side fluctuations on the channel gets minimized, improves the transconductance and SCEs immunity. 12 The doping concentration in the channel is maintained higher at source side and lower at drain side is referred to as graded channel (GC) FET. 13,14 This kind of doping allows for hot carrier effect (HCE) mitigation and device lifetime improvement owing to the lower drain-side doping concentration, that results in a weaker electric field near the drain region.…”

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confidence: 99%

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Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Mudidhe¹,

Nistala²

2023

ECS J. Solid State Sci. Technol.

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Gate-all around (GAA) device is one of the cutting-edge technologies and the advantages of these devices can be improved by incorporating the dual material (DM) and graded channel (GC) techniques. This manuscript investigates for the first time, the performance analysis of DMGC CGAA FET and circuit applications such as inverter, NAND, NOR, ring oscillator and 6T SRAM. It has been found that the Ioff, SS, DIBL, Ion/Ioff ratio are enhanced by an amount of 96.93%, 19.49%, 51.26%, 96.98% respectively for DMGC CGAA FET when compared to SMGC CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93%, 11.25%, and 10.07% respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7% with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

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Section: T E O T T K39 1 High K Imentioning

confidence: 99%

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confidence: 99%

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Mudidhe¹,

Nistala²

2023

ECS J. Solid State Sci. Technol.

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“…A. Tsormpatzoglou et al [26] performed a comparison of rectangular and cylindrical GAA FETs and observed that the cylindrical device performs significantly better than the rectangular device. Recently, we have reported the enhanced threshold voltage characteristics of a DMGC CGAA MOSFET [27] by combining the benefits of DM gate engineering and the concepts of GC channel engineering. In this paper, the analytical drain current model of the proposed device is presented in linear and saturation region.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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“…For getting better performance in semiconductor device, the researchers have proposed the novel devices like double gate (DG) FET, FINFET, quadruple gate (QG) FINFET, and gate all around (GAA) FETs to minimize the SCEs. 3,4 However, CGAA FET is one among the assuring contender to control the SCEs as its channel has better gate control. There are different methods like material, gate and channel engineering to enhance the efficiency of the CGAA FET.…”

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confidence: 99%

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

Mudidhe

Nistala

2023

ECS J. Solid State Sci. Technol.

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This manuscript introduces a pioneering investigation on the temperature effects of Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET by outlining its significance in various aspects such as analog/RF, self-heating, and linearity performance metrics. For this analysis, we have proposed a DMGC CGAA FET by amalgamating the gate and channel engineering techniques and the temperature is varied from 250K to 450K. A significant improvement in Ion/Ioff, SS, and DIBL by an amount of 96.98%, 19.49%, and 51.26% is obtained respectively for the proposed DMGC CGAA FET as compared to the single material graded channel (SMGC) CGAA FET. As the temperature is reduced from 450K to 250K, a noticeable improvement in analog/RF figure of merits and delay is obtained. Further, the self-heating effect (SHE) analysis revealed that the utilization of lower Rth is preferrable to minimize SHE in the device. Moreover, linearity parameters like gm2, gm3, VIP2, VIP3, IIP3 and IMD3 are noticed to be better for lower temperatures at higher VGS indicating good linearity. The obtained results make proposed device an ideal choice for various applications especially that operate in low temperature environments such as deep space, military, and RF applications.

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Analytical modeling of a dual-material graded-channel cylindrical gate-all-around FET to minimize the short-channel effects

Cited by 5 publications

References 42 publications

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

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