Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

Schwantes, S.; Florian, T.; Stephan, Thompson; Gräf, M.; Dudek, V.

doi:10.1109/ted.2005.850952

Cited by 31 publications

(21 citation statements)

References 9 publications

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“…As for the analytical models for SOI devices, Chung et al have given a model of the surface electric field distributions only for the fully-depleted SOI devices accounting for the effects of the gate and drain field plate [10], based on which, the analytical model for the breakdown voltage of both the fully-depleted and partiallydepleted SOI devices taking account of the back-gate effect has been presented in Ref. [11]. The breakdown model and RESURF condition for SOI device with step drift doping profile have been given [12].…”

Section: Introductionmentioning

confidence: 99%

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Luo

Zhang

2007

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Luo

Zhang

2007

Solid-State Electronics

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“…Some techniques have been developed to improve the vertical breakdown characteristic such as the floating buried layer in substrate [4], REBULF technology [5] and silicon on insulator (SOI) [6]. The back-gate technology can improve the breakdown behaviour of an SOI device through the field modulation of interface charges by back-gate bias, which is not suitable for the conventional silicon device since there exists a vertical conduction path in the off-state [7,8]. In this Letter, a novel double p 2 /n + layer substrate LDMOS structure using substrate bias technology with improved characteristic of BV and on-resistance is proposed for the first time.…”

mentioning

confidence: 99%

High voltage silicon power device structure with substrate bias

Wang

et al. 2011

Electronics Letters

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A new high voltage silicon LDMOS structure with substrate bias is reported (SB S-LDMOS). The vertical conduction path is blocked by the double p 2 /n + layer substrate when positive substrate bias is applied to the SB S-LDMOS. The bulk electric field in the drift region redistributes by substrate bias and the vertical voltage sustained by the depletion region under drain decreases significantly, which is especially important for a thin drift region power device. Numerical results indicate that the breakdown voltage of the proposed device is increased by 94% compared to conventional LDMOS, while maintaining low on-resistance.Introduction: One of the most popular high-voltage devices is the lateral double diffused MOS transistor (LDMOS). To be feasibly isolated from low-voltage devices, an LDMOS needs a thin drift region and to satisfy the reduced surface field (RESURF) principle [1]. The recent development of the LDMOS has concentrated on improving the trade-off between breakdown voltage (BV) and on-resistance [2,3]. For the conventional thin drift device the vertical BV is the main element that limits the device's blocking capability. Some techniques have been developed to improve the vertical breakdown characteristic such as the floating buried layer in substrate [4], REBULF technology [5] and silicon on insulator (SOI) [6].

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“…In fact, breakdown voltage of SOI can profit from a positive back-gate voltage without enhancing the vertical breakdown voltage. However, a large positive back-gate voltage reduces the RESURF effect and results in increasing the on-resistance and decreasing drastically breakdown voltage [7]. …”

mentioning

confidence: 99%

A new back-gate SOI high voltage device with a compound layer

Yang

Zhang

Luo

et al. 2009

2009 International Conference on Applied Superconductivity and Electromagnetic Devices

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A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance. The breakdown voltage and electric field profile are researched for the new structure by using 2D MEDICI software. Simulation result shows that BG CL SOI-LDMOS can reach 557 V, 165.8 % higher than conventional SOI, at 1 m-thick buried oxide layer 40 m-length drift region and 240V back-gate voltage. Keywords-silicon on insulator; breakdown voltage; compound layer I. INTRODUCTIONPower devices fabricated on silicon-on-insulator (SOI) substrate have many attractive virtues, such as ideal dielectric isolation, low leakage current near ideal isolation and high switching speed. However, breakdown voltage of SOI (siliconon-insulator) is very difficult to achieve over 600 V due to limitation of vertical breakdown voltage. To enhance the vertical breakdown voltage, effective methods have been proposed, such as ENDIF (enhanced dielectric layer field) [1][2][3][4] and PSOI (Partial SOI) [5], [6]. In fact, breakdown voltage of SOI can profit from a positive back-gate voltage without enhancing the vertical breakdown voltage. However, a large positive back-gate voltage reduces the RESURF effect and results in increasing the on-resistance and decreasing drastically breakdown voltage [7].

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Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

Cited by 31 publications

References 9 publications

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

High voltage silicon power device structure with substrate bias

A new back-gate SOI high voltage device with a compound layer

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