Abstract:A new high voltage silicon LDMOS structure with substrate bias is reported (SB S-LDMOS). The vertical conduction path is blocked by the double p 2 /n + layer substrate when positive substrate bias is applied to the SB S-LDMOS. The bulk electric field in the drift region redistributes by substrate bias and the vertical voltage sustained by the depletion region under drain decreases significantly, which is especially important for a thin drift region power device. Numerical results indicate that the breakdown vo… Show more
“…Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”
mentioning
confidence: 99%
“…Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”
A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 mm, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this new structure, a high ESD failure current of 4.4 A was achieved with a total channel width of only 60 mm. Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices. However, these LDMOS-based driver circuits are still vulnerable to ESD stresses, which are often attributed to the inhomogeneous triggering of the parasitic bipolar junction transitor (BJT) and base push-out effect [3]. The designs of LDMOS-based ESD clamps, as well as the self-protection scheme of an LDMOS output driver are still challenging issues [4].A promising technique to sidestep these weaknesses is to use an embedded sillicon controlled rectifier (SCR) in the LDMOS structure (LDMOS-SCR) [5]. The LDMOS-SCR goes into the SCR mode under a high voltage or a large current condition. The traditional layout employs the stripe style. In this Letter, a novel waffle layout LDMOS-SCR structure is proposed and the performance is verified with a 0.35 mm 30/5 V BCD process. We found that the device with this structure has better robustness and consumes less silicon area and thus has high practical values.
“…Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”
mentioning
confidence: 99%
“…Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices.…”
A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 mm, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this new structure, a high ESD failure current of 4.4 A was achieved with a total channel width of only 60 mm. Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.Introduction: Laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor arrays are widely used as output drivers in highvoltage (HV) circuits such as power management applications, lightemitting diode (LED) and liquid-crystal display (LCD) driver circuits [1,2]. To achieve a high-voltage operation and a high current driven capability, the sizes of LDMOS transistors, typically with widths over 10000 mm, are much larger than those of other CMOS devices. However, these LDMOS-based driver circuits are still vulnerable to ESD stresses, which are often attributed to the inhomogeneous triggering of the parasitic bipolar junction transitor (BJT) and base push-out effect [3]. The designs of LDMOS-based ESD clamps, as well as the self-protection scheme of an LDMOS output driver are still challenging issues [4].A promising technique to sidestep these weaknesses is to use an embedded sillicon controlled rectifier (SCR) in the LDMOS structure (LDMOS-SCR) [5]. The LDMOS-SCR goes into the SCR mode under a high voltage or a large current condition. The traditional layout employs the stripe style. In this Letter, a novel waffle layout LDMOS-SCR structure is proposed and the performance is verified with a 0.35 mm 30/5 V BCD process. We found that the device with this structure has better robustness and consumes less silicon area and thus has high practical values.
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