A new high voltage silicon LDMOS structure with substrate bias is reported (SB S-LDMOS). The vertical conduction path is blocked by the double p 2 /n + layer substrate when positive substrate bias is applied to the SB S-LDMOS. The bulk electric field in the drift region redistributes by substrate bias and the vertical voltage sustained by the depletion region under drain decreases significantly, which is especially important for a thin drift region power device. Numerical results indicate that the breakdown voltage of the proposed device is increased by 94% compared to conventional LDMOS, while maintaining low on-resistance.Introduction: One of the most popular high-voltage devices is the lateral double diffused MOS transistor (LDMOS). To be feasibly isolated from low-voltage devices, an LDMOS needs a thin drift region and to satisfy the reduced surface field (RESURF) principle [1]. The recent development of the LDMOS has concentrated on improving the trade-off between breakdown voltage (BV) and on-resistance [2,3]. For the conventional thin drift device the vertical BV is the main element that limits the device's blocking capability. Some techniques have been developed to improve the vertical breakdown characteristic such as the floating buried layer in substrate [4], REBULF technology [5] and silicon on insulator (SOI) [6].
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