A new back-gate SOI high voltage device with a compound layer

Abstract

A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance. The breakdown voltage and electric field profile are researched for the new structure by using 2D MEDICI software. Simulation result shows that BG CL SOI-LDMOS can reach 557 V, 165.8 % higher than conventional SOI, at 1 m-thick buried oxide layer 40 m-length drift region and 240V back-gate voltage. Keywords-silicon on insulator; breakdown voltage; compound layer I. INTRODUCTIONPower devices fabricated on silicon-on-insulator (SOI) substrate have many attractive virtues, such as ideal dielectric isolation, low leakage current near ideal isolation and high switching speed. However, breakdown voltage of SOI (siliconon-insulator) is very difficult to achieve over 600 V due to limitation of vertical breakdown voltage. To enhance the vertical breakdown voltage, effective methods have been proposed, such as ENDIF (enhanced dielectric layer field) [1][2][3][4] and PSOI (Partial SOI) [5], [6]. In fact, breakdown voltage of SOI can profit from a positive back-gate voltage without enhancing the vertical breakdown voltage. However, a large positive back-gate voltage reduces the RESURF effect and results in increasing the on-resistance and decreasing drastically breakdown voltage [7].